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    Technologies for secure programming of a cryptographic engine for trusted I/O
    11.
    发明授权
    Technologies for secure programming of a cryptographic engine for trusted I/O 有权

    公开(公告)号：US10303900B2

    公开(公告)日：2019-05-28

    申请号：US14979002

    申请日：2015-12-22

    Applicant: INTEL CORPORATION

    Inventor： Siddhartha Chhabra ,  Gideon Gerzon ,  Reshma Lal ,  Bin Xing ,  Pradeep M. Pappachan ,  Steven B. McGowan

    IPC: H04L9/08 ,  H04L9/32 ,  G06F21/72 ,  G06F21/57

    Abstract: Technologies for secure programming of a cryptographic engine include a computing device with a cryptographic engine and one or more I/O controllers. The computing device establishes, an invoking secure enclave using secure enclave support of a processor. The invoking enclave configures channel programming information, including a channel key, and invokes a processor instruction with the channel programming information as a parameter. The processor generates wrapped programming information including an encrypted channel key and a message authentication code. The encrypted channel key is protected with a key known only to the processor. The invoking enclave provides the wrapped programming information to untrusted software, which invokes a processor instruction with the wrapped programming information as a parameter. The processor unwraps and verifies the wrapped programming information and then programs the cryptographic engine. The processor generates an authenticated response that may be verified by the invoking enclave. Other embodiments are described and claimed.

    Technologies for secure hardware and software attestation for trusted I/O
    13.
    发明授权
    Technologies for secure hardware and software attestation for trusted I/O 有权

    公开(公告)号：US10248791B2

    公开(公告)日：2019-04-02

    申请号：US14974960

    申请日：2015-12-18

    Applicant: Intel Corporation

    Inventor： Pradeep M. Pappachan ,  Reshma Lal ,  Bin Xing ,  Siddhartha Chhabra ,  Vincent R. Scarlata ,  Steven B. McGowan

    IPC: G06F21/57 ,  G06F13/28 ,  G06F21/60

    Abstract: Technologies for trusted I/O attestation and verification include a computing device with a cryptographic engine and one or more I/O controllers. The computing device collects hardware attestation information associated with statically attached hardware I/O components that are associated with a trusted I/O usage protected by the cryptographic engine. The computing device verifies the hardware attestation information and securely enumerates one or more dynamically attached hardware components in response to verification. The computing device collects software attestation information for trusted software components loaded during secure enumeration. The computing device verifies the software attestation information. The computing device may collect firmware attestation information for firmware loaded in the I/O controllers and verify the firmware attestation information. The computing device may collect application attestation information for a trusted application that uses the trusted I/O usage and verify the application attestation information. Other embodiments are described and claimed.

    INTEGRITY PROTECTED COMMAND BUFFER EXECUTION
    16.
    发明申请
    INTEGRITY PROTECTED COMMAND BUFFER EXECUTION 有权

    公开(公告)号：US20250125966A1

    公开(公告)日：2025-04-17

    申请号：US18990178

    申请日：2024-12-20

    Applicant: Intel Corporation

    Inventor： Pradeep M. Pappachan ,  Reshma Lal

    IPC: H04L9/32 ,  G06F21/60 ,  H04L9/08

    Abstract: Embodiments are directed to providing integrity-protected command buffer execution. An embodiment of an apparatus includes a computer-readable memory comprising one or more command buffers and a processing device communicatively coupled to the computer-readable memory to read, from a command buffer of the computer-readable memory, a first command received from a host device, the first command executable by one or more processing elements on the processing device, the first command comprising an instruction and associated parameter data, compute a first authentication tag using a cryptographic key associated with the host device, the instruction and at least a portion of the parameter data, and authenticate the first command by comparing the first authentication tag with a second authentication tag computed by the host device and associated with the command.

    INTEGRITY PROTECTED COMMAND BUFFER EXECUTION
    20.
    发明公开
    INTEGRITY PROTECTED COMMAND BUFFER EXECUTION 审中-公开

    公开(公告)号：US20240121097A1

    公开(公告)日：2024-04-11

    申请号：US18391375

    申请日：2023-12-20

    Applicant: Intel Corporation

    Inventor： Pradeep M. Pappachan ,  Reshma Lal

    IPC: H04L9/32 ,  G06F21/60 ,  H04L9/08

    CPC classification number: H04L9/3226 ,  G06F21/602 ,  H04L9/085

    Abstract: Embodiments are directed to providing integrity-protected command buffer execution. An embodiment of an apparatus includes a computer-readable memory comprising one or more command buffers and a processing device communicatively coupled to the computer-readable memory to read, from a command buffer of the computer-readable memory, a first command received from a host device, the first command executable by one or more processing elements on the processing device, the first command comprising an instruction and associated parameter data, compute a first authentication tag using a cryptographic key associated with the host device, the instruction and at least a portion of the parameter data, and authenticate the first command by comparing the first authentication tag with a second authentication tag computed by the host device and associated with the command.

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