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    Extending a root complex to encompass an external component
    3.
    发明授权
    Extending a root complex to encompass an external component 有权

    公开(公告)号：US10789370B2

    公开(公告)日：2020-09-29

    申请号：US15470270

    申请日：2017-03-27

    Applicant: INTEL CORPORATION

    Inventor： Mohan K. Nair ,  Rajesh M. Sankaran ,  Utkarsh Y. Kakaiya ,  Zhenfu Chai ,  David M. Lee ,  Pratik M. Marolia

    IPC: G06F9/4401 ,  G06F21/60 ,  G06F21/85 ,  G06F21/57 ,  G06F12/0815 ,  G06F13/42 ,  H04L29/06

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.

    Method, apparatus, system for centering in a high performance interconnect
    4.
    发明授权
    Method, apparatus, system for centering in a high performance interconnect 有权

    公开(公告)号：US10560081B2

    公开(公告)日：2020-02-11

    申请号：US15632836

    申请日：2017-06-26

    Applicant: Intel Corporation

    Inventor： Mahesh Wagh ,  Zuoguo J. Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Todd A. Hinck ,  David M. Lee ,  Narasimha R. Lanka

    IPC: H03K5/26 ,  G01R31/04 ,  H03L9/00 ,  G06F1/3296 ,  G06F13/42 ,  H03K5/131

    Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

    Data transfer between asynchronous clock domains
    10.
    发明授权
    Data transfer between asynchronous clock domains 有权

    公开(公告)号：US10599178B2

    公开(公告)日：2020-03-24

    申请号：US16036419

    申请日：2018-07-16

    Applicant: Intel Corporation

    Inventor： Michael C. Rifani ,  Alan B. Kyker ,  Alan S. Geist ,  David M. Lee

    IPC: G06F1/12 ,  G06F13/42

    Abstract: Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

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