Abstract:
A host machine includes a guest machine, a device emulator, and a hypervisor communicably coupled to the guest machine and the device emulator. The guest machine executes a non-real time thread that causes a non-real time I/O emulation by the device emulator. Responsive to receipt of a real time thread by the guest machine, the hypervisor determines whether the non-real time I/O emulation is abortable or non-abortable. If abortable, the hypervisor aborts the non-real time thread and causes the guest machine to execute the real time thread. Upon completing the execution of the real time thread, the hypervisor causes the guest machine to revert to a non-real time context based on a previous system snapshot. Upon establishing the non-real time context, the hypervisor causes the guest machine to execute the previously aborted non-real time thread.
Abstract:
It includes techniques to provide for reliable primary and secondary containers arranged to separately execute an application that receives request packets for processing by the application. The request packets may be received from a client coupled with a server arranged to host the primary container or the secondary container. The client coupled with the server through a network. Coarse-grained lock-stepping (COLO) methods may be utilized to facilitate in providing the reliable primary and secondary containers.
Abstract:
Generally, this disclosure describes systems (and methods) of moderating interrupts in a virtualization environment. An overflow interval is defined. The overflow interrupt interval is used to trigger activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.