公开(公告)号：US20150001585A1

公开(公告)日：2015-01-01

申请号：US14486108

申请日：2014-09-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02112 ,  H01L21/02532 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66568 ,  H01L29/66636

Abstract: In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.

公开(公告)号：US20140349451A1

公开(公告)日：2014-11-27

申请号：US14292312

申请日：2014-05-30

Applicant: International Business Machines Corporation

Inventor： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/306 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/823871 ,  H01L21/28079 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/4958

Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

Abstract translation: 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

公开(公告)号：US08835234B2

公开(公告)日：2014-09-16

申请号：US13916925

申请日：2013-06-13

Applicant: International Business Machines Corporation

Inventor： Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC: H01L21/8238 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66651

Abstract: A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.

Abstract translation: 通过在硅表面上沉积硅碳合金层，在硅表面上提供硅的δ掺杂，硅表面可以是体硅衬底的水平表面，绝缘体上半导体衬底的顶部硅层的水平表面， 或硅片的垂直表面。 可以通过在PFET区域中而不是在NFET区域中选择性地沉积硅锗合金层来区分p型场效应晶体管（PFET）区域和n型场效应晶体管（NFET）区域。 PFET区域中的硅锗合金层可以覆盖或叠加在硅碳合金层上。 普通材料堆叠可用于PFET和NFET的栅极电介质和栅电极。 PFET和NFET的每个沟道包括硅碳合金层，并且通过硅锗层的存在或不存在来区分。

公开(公告)号：US08779469B2

公开(公告)日：2014-07-15

申请号：US14080931

申请日：2013-11-15

Applicant: International Business Machines Corporation

Inventor： Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC: H01L21/02

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76801 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834

Abstract: Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.

Abstract translation: 掺杂的阱，栅极堆叠和嵌入的源极和漏极区域形成在半导体衬底上或之中，随后在半导体衬底中形成浅沟槽。 可以通过在掺杂阱，栅极堆叠和嵌入的源极和漏极区域上形成平坦化材料层来形成浅沟槽; 图案化平坦化材料层; 并将平坦化材料层中的图案转移到栅极堆叠，嵌入的源极和漏极区以及掺杂阱中。 浅沟槽用电介质材料填充以形成浅沟槽隔离结构。 或者，可以通过在掺杂阱，栅极堆叠以及嵌入的源极和漏极区域上施加光刻胶，然后蚀刻下面的结构的暴露部分来形成浅沟槽。 去除光致抗蚀剂后，可以通过填充浅沟槽形成浅沟槽隔离结构。