公开(公告)号：US09349609B2

公开(公告)日：2016-05-24

申请号：US14230065

申请日：2014-03-31

Applicant: International Business Machines Corporation

Inventor： Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC: H01L21/324 ,  H01L21/3205 ,  H01L29/66

CPC classification number: H01L21/324 ,  H01L21/32051 ,  H01L21/32055 ,  H01L29/66545

Abstract: A method including forming a structure including a plurality of semiconductor devices surrounded by a dielectric layer such that a top surface of the dielectric layer is substantially flush with a top surface of the plurality of semiconductor devices, depositing a thermal optimization layer above the structure, patterning the thermal optimization layer such that a portion of the thermal optimization layer is removed from a above first region of the structure and another portion of the thermal optimization layer remains above a second region of the structure, the first region having a different thermal conductivity than the second region, and heating the structure, the patterned thermal optimization layer causing substantially uniform thermal absorption of the structure.

Abstract translation: 一种方法，包括形成包括由电介质层包围的多个半导体器件的结构，使得电介质层的顶表面与多个半导体器件的顶表面基本齐平，在结构上方沉积热优化层，图案化 所述热优化层使得所述热优化层的一部分从所述结构的上述第一区域移除，并且所述热优化层的另一部分保留在所述结构的第二区域的上方，所述第一区域具有不同于所述结构的第二区域的热导率 第二区域，并且加热该结构，图案化热优化层引起结构的基本均匀的热吸收。

公开(公告)号：US20150349089A1

公开(公告)日：2015-12-03

申请号：US14820938

申请日：2015-08-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02112 ,  H01L21/02532 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66568 ,  H01L29/66636

Abstract: In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.

Abstract translation: 在一个实施例中，提供了半导体器件，其包括半导体衬底，该半导体衬底包括有源区和位于有源区的周边的至少一个沟槽隔离区，以及存在于半导体衬底的有源区的一部分上的功能栅结构 。 嵌入式半导体区域存在于半导体衬底的有源区域中，在有源区域的存在功能栅极结构的部分的相对侧上。 半导体衬底的有源区域的一部分将嵌入的半导体区域的最外边缘与至少一个隔离区域分开。 还提供了形成上述装置的方法。

公开(公告)号：US08993389B2

公开(公告)日：2015-03-31

申请号：US13734012

申请日：2013-01-04

Applicant: International Business Machines Corporation

Inventor： Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28 ,  H01L21/28123 ,  H01L27/0207 ,  H01L29/78

Abstract: A method of forming a semiconductor device comprising a dummy gate interconnect includes forming a dummy gate on a substrate, the dummy gate comprising a dummy gate metal layer located on the substrate, and a dummy gate polysilicon layer located on the dummy gate metal layer; forming an active gate on the substrate, the active gate comprising an active gate metal layer located on the substrate, and an active gate polysilicon layer located on the active gate metal layer; and etching the dummy gate polysilicon layer to remove at least a portion of the dummy gate polysilicon layer to form the dummy gate interconnect, wherein the active gate polysilicon layer is not etched during the etching of the dummy gate polysilicon layer.

Abstract translation: 一种形成包括伪栅极互连的半导体器件的方法包括在衬底上形成虚拟栅极，所述伪栅极包括位于所述衬底上的伪栅极金属层和位于所述伪栅极金属层上的伪栅极多晶硅层; 在所述衬底上形成有源栅极，所述有源栅极包括位于所述衬底上的有源栅极金属层和位于所述有源栅极金属层上的有源栅极多晶硅层; 并且蚀刻伪栅极多晶硅层以去除伪栅极多晶硅层的至少一部分以形成伪栅极互连，其中在伪栅极多晶硅层的蚀刻期间不蚀刻有源栅极多晶硅层。

公开(公告)号：US20140191295A1

公开(公告)日：2014-07-10

申请号：US13734012

申请日：2013-01-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28 ,  H01L21/28123 ,  H01L27/0207 ,  H01L29/78

Abstract: A method of forming a semiconductor device comprising a dummy gate interconnect includes forming a dummy gate on a substrate, the dummy gate comprising a dummy gate metal layer located on the substrate, and a dummy gate polysilicon layer located on the dummy gate metal layer; forming an active gate on the substrate, the active gate comprising an active gate metal layer located on the substrate, and an active gate polysilicon layer located on the active gate metal layer; and etching the dummy gate polysilicon layer to remove at least a portion of the dummy gate polysilicon layer to form the dummy gate interconnect, wherein the active gate polysilicon layer is not etched during the etching of the dummy gate polysilicon layer.

Abstract translation: 一种形成包括伪栅极互连的半导体器件的方法包括在衬底上形成虚拟栅极，所述伪栅极包括位于所述衬底上的伪栅极金属层和位于所述伪栅极金属层上的伪栅极多晶硅层; 在所述衬底上形成有源栅极，所述有源栅极包括位于所述衬底上的有源栅极金属层和位于所述有源栅极金属层上的有源栅极多晶硅层; 并且蚀刻伪栅极多晶硅层以去除伪栅极多晶硅层的至少一部分以形成伪栅极互连，其中在伪栅极多晶硅层的蚀刻期间不蚀刻有源栅极多晶硅层。

公开(公告)号：US20140070274A1

公开(公告)日：2014-03-13

申请号：US14080931

申请日：2013-11-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76801 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834

Abstract: Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.

Abstract translation: 掺杂的阱，栅极堆叠和嵌入的源极和漏极区域形成在半导体衬底上或之中，随后在半导体衬底中形成浅沟槽。 可以通过在掺杂阱，栅极堆叠和嵌入的源极和漏极区域上形成平坦化材料层来形成浅沟槽; 图案化平坦化材料层; 并将平坦化材料层中的图案转移到栅极堆叠，嵌入的源极和漏极区以及掺杂阱中。 浅沟槽用电介质材料填充以形成浅沟槽隔离结构。 或者，可以通过在掺杂阱，栅极堆叠和嵌入的源极和漏极区域上施加光刻胶，然后蚀刻下面的结构的暴露部分来形成浅沟槽。 去除光致抗蚀剂后，可以通过填充浅沟槽形成浅沟槽隔离结构。

公开(公告)号：US20130273699A1

公开(公告)日：2013-10-17

申请号：US13916925

申请日：2013-06-13

Applicant: International Business Machines Corporation

Inventor： Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC: H01L21/8238

CPC classification number: H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66651

Abstract: A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.

Abstract translation: 通过在硅表面上沉积硅碳合金层，在硅表面上提供硅的δ掺杂，硅表面可以是体硅衬底的水平表面，绝缘体上半导体衬底的顶部硅层的水平表面， 或硅片的垂直表面。 可以通过在PFET区域中而不是在NFET区域中选择性地沉积硅锗合金层来区分p型场效应晶体管（PFET）区域和n型场效应晶体管（NFET）区域。 PFET区域中的硅锗合金层可以覆盖或叠加在硅碳合金层上。 普通材料堆叠可用于PFET和NFET的栅极电介质和栅电极。 PFET和NFET的每个沟道包括硅碳合金层，并且通过硅锗层的存在或不存在来区分。

公开(公告)号：US09105722B2

公开(公告)日：2015-08-11

申请号：US14486108

申请日：2014-09-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/02112 ,  H01L21/02532 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66568 ,  H01L29/66636

Abstract: In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.

Abstract translation: 在一个实施例中，提供了半导体器件，其包括半导体衬底，该半导体衬底包括有源区和位于有源区的周边的至少一个沟槽隔离区，以及存在于半导体衬底的有源区的一部分上的功能栅结构 。 嵌入式半导体区域存在于半导体衬底的有源区域中，在有源区域的存在功能栅极结构的部分的相对侧上。 半导体衬底的有源区域的一部分将嵌入的半导体区域的最外边缘与至少一个隔离区域分开。 还提供了形成上述装置的方法。

公开(公告)号：US20140123097A1

公开(公告)日：2014-05-01

申请号：US14148234

申请日：2014-01-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jeae-Eun Park ,  Kern Rim ,  Xiaojun Yu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G01R31/2848 ,  G01R31/3008 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5036

Abstract: A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

Abstract translation: 一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。 泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。 泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。 泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。 该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

公开(公告)号：US20150279692A1

公开(公告)日：2015-10-01

申请号：US14230065

申请日：2014-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC: H01L21/324 ,  H01L29/66 ,  H01L21/3205

CPC classification number: H01L21/324 ,  H01L21/32051 ,  H01L21/32055 ,  H01L29/66545

Abstract: A method including forming a structure including a plurality of semiconductor devices surrounded by a dielectric layer such that a top surface of the dielectric layer is substantially flush with a top surface of the plurality of semiconductor devices, depositing a thermal optimization layer above the structure, patterning the thermal optimization layer such that a portion of the thermal optimization layer is removed from a above first region of the structure and another portion of the thermal optimization layer remains above a second region of the structure, the first region having a different thermal conductivity than the second region, and heating the structure, the patterned thermal optimization layer causing substantially uniform thermal absorption of the structure.

Abstract translation: 一种方法，包括形成包括由电介质层包围的多个半导体器件的结构，使得电介质层的顶表面与多个半导体器件的顶表面基本齐平，在结构上方沉积热优化层，图案化 所述热优化层使得所述热优化层的一部分从所述结构的上述第一区域移除，并且所述热优化层的另一部分保留在所述结构的第二区域的上方，所述第一区域具有不同于所述结构的第二区域的热导率 第二区域，并且加热该结构，图案化热优化层引起结构的基本均匀的热吸收。

公开(公告)号：US09082877B2

公开(公告)日：2015-07-14

申请号：US14292312

申请日：2014-05-30

Applicant: International Business Machines Corporation

Inventor： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/306 ,  H01L21/762 ,  H01L29/49

CPC classification number: H01L21/823871 ,  H01L21/28079 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/4958

Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

Abstract translation: 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。