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公开(公告)号：US11467840B2
公开(公告)日：2022-10-11
申请号：US16743586
申请日：2020-01-15
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
Abstract: Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.
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公开(公告)号：US20220277124A1
公开(公告)日：2022-09-01
申请号：US17749054
申请日：2022-05-19
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.
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公开(公告)号：US20220139480A1
公开(公告)日：2022-05-05
申请号：US17573542
申请日：2022-01-11
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.
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公开(公告)号：US11030039B2
公开(公告)日：2021-06-08
申请号：US17028253
申请日：2020-09-22
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
IPC: G06F11/00 , G06F11/07 , G06F30/30 , G06F30/392 , G06F115/10 , G06F117/06
Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.
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公开(公告)号：US10755011B2
公开(公告)日：2020-08-25
申请号：US15784353
申请日：2017-10-16
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
IPC: G06F30/3323 , G06F11/07 , G06F11/34 , G06F30/39
Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.
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Patent Agency Ranking
公开(公告)号：US20170133104A1
公开(公告)日：2017-05-11
申请号：US15340726
申请日：2016-11-01
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.
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公开(公告)号：US20240411972A1
公开(公告)日：2024-12-12
申请号：US18807813
申请日：2024-08-16
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
IPC: G06F30/3323 , G06F11/07 , G06F11/34 , G06F30/39
Abstract: A formal verification tool used with a hardware monitor to verify that a hardware design for an electronic device does not comprise a bug or error that can cause an instantiation of the hardware design to fetch an instruction from an out-of-bounds address. Formal assertations for a hardware design are received, wherein the formal assertions assert a formal property that compares a memory address from which an instruction was fetched by an instantiation of the hardware design to an allowable memory address range or an unallowable memory address range associated with an operating state of the instantiation of the hardware design when the fetch was performed. The tool formally verifies that the formal assertations are true for the hardware design to identify whether the hardware design has a bug or error that causes an out-of-bounds violation.
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公开(公告)号：US20230094774A1
公开(公告)日：2023-03-30
申请号：US18076231
申请日：2022-12-06
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
IPC: G06F30/3323 , G06F11/36 , G06F11/34 , G06F30/39 , G06F30/30 , G06F11/30 , G06F119/18
Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.
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公开(公告)号：US20210182463A1
公开(公告)日：2021-06-17
申请号：US17184186
申请日：2021-02-24
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.
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公开(公告)号：US20210165942A1
公开(公告)日：2021-06-03
申请号：US17168945
申请日：2021-02-05
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
IPC: G06F30/3323 , G06F11/07 , G06F11/34 , G06F30/39
Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.
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