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公开(公告)号：US10459784B2
公开(公告)日：2019-10-29
申请号：US13930132
申请日：2013-06-28
Applicant: Infineon Technologies AG
Inventor： Bernhard Gstöttenbauer , Klemens Kordik
IPC: G06F11/10
Abstract: A frequency signal generator includes a controllable oscillator unit, a frequency control unit and an error detection unit. The controllable oscillator unit generates and provides a frequency signal. The frequency control unit generates a frequency control signal and the controllable oscillator unit varies a frequency of the frequency signal based on the frequency control signal. Further, the error detection unit receives the frequency control signal, detects an error within the frequency control signal and provides an error signal. The error signal comprises information on a detected error.
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Patent Agency Ranking
公开(公告)号：US10223507B2
公开(公告)日：2019-03-05
申请号：US15337343
申请日：2016-10-28
Applicant: Infineon Technologies AG
Inventor： Klemens Kordik
Abstract: A programmable system with program flow monitoring is provided. A memory is configured to store a set of instructions, where the instructions are configured to be executed in a predefined order. A processor is configured to execute the set of instructions by fetching and executing the instructions in the predefined order. A program flow monitoring (PFM) unit is configured to deterministically generate a fingerprint from accesses to the memory, such as instruction fetches, while executing the set of instructions. A verification unit is configured to compare the generated fingerprint to an expected fingerprint to determine whether the set of instructions executed in the predefined order. A method for program flow monitoring, as well as a safety system within which the programmable system finds application, are also provided.
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公开(公告)号：US09485036B2
公开(公告)日：2016-11-01
申请号：US15099130
申请日：2016-04-14
Applicant: Infineon Technologies AG
Inventor： Klemens Kordik , Rainer Stuhlberger
CPC classification number: H04B17/0085 , H04B17/14 , H04B17/17 , H04B17/23 , H04B17/29 , H04L7/0054
Abstract: An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion.
Abstract translation: RF接收器件包括芯片封装中的半导体芯片和集成在芯片中的测试信号发生器。 测试信号发生器产生包括第一信息的RF测试信号。 集成在芯片中的RF接收器电路接收RF输入信号，将RF输入信号下变频为中频（IF）或基带，并将下变频信号数字化以获得数字信号。 RF接收信道包括具有第一和第二输入端口和输出端口的耦合器。 输出端口耦合到RF接收器电路的输入端，第一输入端口接收天线信号，第二输入端口从测试信号发生器接收测试信号。 信号处理器集成在芯片中，并且在测试周期期间确定数字信号中的第一信息是否匹配预定标准。
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公开(公告)号：US09385700B2
公开(公告)日：2016-07-05
申请号：US14497360
申请日：2014-09-26
Applicant: Infineon Technologies AG
Inventor： Klemens Kordik , Bernhard Gstoettenbauer , Klaus Buchner , Thomas Sailer
Abstract: A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator and a comparator circuit. The pulse generator is configured to generate a sequence of pulses synchronous to the clock signal, wherein each pulse has an edge with a monotonously rising or falling signal level. The comparator circuit receives the sequence of pulses and is configured to detect, for each clock cycle of the clock signal, whether or not the signal level of the sequence of pulses is outside a desired range at a specific time instant within the clock cycle of the clock signal.
Abstract translation: 描述用于监视时钟信号的监视电路。 根据本公开的一个示例，监视电路包括脉冲发生器和比较器电路。 脉冲发生器被配置为产生与时钟信号同步的脉冲序列，其中每个脉冲具有单调上升或下降信号电平的边沿。 比较器电路接收脉冲序列，并被配置为在时钟信号的每个时钟周期内检测脉冲序列的信号电平是否在该时钟周期内的特定时刻在期望范围之外 时钟信号。
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公开(公告)号：US20160094212A1
公开(公告)日：2016-03-31
申请号：US14497360
申请日：2014-09-26
Applicant: Infineon Technologies AG
Inventor： Klemens Kordik , Bernhard Gstoettenbauer , Klaus Buchner , Thomas Sailer
Abstract: A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator and a comparator circuit. The pulse generator is configured to generate a sequence of pulses synchronous to the clock signal, wherein each pulse has an edge with a monotonously rising or falling signal level. The comparator circuit receives the sequence of pulses and is configured to detect, for each clock cycle of the clock signal, whether or not the signal level of the sequence of pulses is outside a desired range at a specific time instant within the clock cycle of the clock signal.
Abstract translation: 描述用于监视时钟信号的监视电路。 根据本公开的一个示例，监视电路包括脉冲发生器和比较器电路。 脉冲发生器被配置为产生与时钟信号同步的脉冲序列，其中每个脉冲具有单调上升或下降信号电平的边沿。 比较器电路接收脉冲序列，并且被配置为在时钟信号的每个时钟周期内检测脉冲序列的信号电平是否在该时钟周期内的特定时刻在期望范围之外 时钟信号。
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公开(公告)号：US20160087734A1
公开(公告)日：2016-03-24
申请号：US14493610
申请日：2014-09-23
Applicant: Infineon Technologies AG
Inventor： Klemens Kordik , Rainer Stuhlberger
CPC classification number: H04B17/0085 , H04B17/14 , H04B17/17 , H04B17/23 , H04B17/29 , H04L7/0054
Abstract: An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion.
Abstract translation: RF接收器件包括芯片封装中的半导体芯片和集成在芯片中的测试信号发生器。 测试信号发生器产生包括第一信息的RF测试信号。 集成在芯片中的RF接收器电路接收RF输入信号，将RF输入信号下变频为中频（IF）或基带，并将下变频信号数字化以获得数字信号。 RF接收信道包括具有第一和第二输入端口和输出端口的耦合器。 输出端口耦合到RF接收器电路的输入端，第一输入端口接收天线信号，第二输入端口从测试信号发生器接收测试信号。 信号处理器集成在芯片中，并且在测试周期期间确定数字信号中的第一信息是否匹配预定标准。
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