公开(公告)号：US20200012556A1

公开(公告)日：2020-01-09

申请号：US16577249

申请日：2019-09-20

Applicant: Infineon Technologies AG

Inventor： Bernhard Gstoettenbauer ,  Klemens Kordik

IPC: G06F11/10

Abstract: A frequency signal generator includes a controllable oscillator unit, a frequency control unit and an error detection unit. The controllable oscillator unit generates and provides a frequency signal. The frequency control unit generates a frequency control signal and the controllable oscillator unit varies a frequency of the frequency signal based on the frequency control signal. Further, the error detection unit receives the frequency control signal, detects an error within the frequency control signal and provides an error signal. The error signal comprises information on a detected error.

公开(公告)号：US20180121272A1

公开(公告)日：2018-05-03

申请号：US15337343

申请日：2016-10-28

Applicant: Infineon Technologies AG

Inventor： Klemens Kordik

IPC: G06F11/07 ,  G06F9/38

CPC classification number: G06F11/36 ,  G06F21/52 ,  G06F21/57 ,  G06F21/64

Abstract: A programmable system with program flow monitoring is provided. A memory is configured to store a set of instructions, where the instructions are configured to be executed in a predefined order. A processor is configured to execute the set of instructions by fetching and executing the instructions in the predefined order. A program flow monitoring (PFM) unit is configured to deterministically generate a fingerprint from accesses to the memory, such as instruction fetches, while executing the set of instructions. A verification unit is configured to compare the generated fingerprint to an expected fingerprint to determine whether the set of instructions executed in the predefined order. A method for program flow monitoring, as well as a safety system within which the programmable system finds application, are also provided.

公开(公告)号：US09331797B2

公开(公告)日：2016-05-03

申请号：US14493610

申请日：2014-09-23

Applicant: Infineon Technologies AG

Inventor： Klemens Kordik ,  Rainer Stuhlberger

IPC: H04B17/00 ,  H04B17/29 ,  H04B17/23

CPC classification number: H04B17/0085 ,  H04B17/14 ,  H04B17/17 ,  H04B17/23 ,  H04B17/29 ,  H04L7/0054

Abstract: An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion.

公开(公告)号：US20160233969A1

公开(公告)日：2016-08-11

申请号：US15099130

申请日：2016-04-14

Applicant: Infineon Technologies AG

Inventor： Klemens Kordik ,  Rainer Stuhlberger

IPC: H04B17/00 ,  H04L7/00 ,  H04B17/14 ,  H04B17/29

CPC classification number: H04B17/0085 ,  H04B17/14 ,  H04B17/17 ,  H04B17/23 ,  H04B17/29 ,  H04L7/0054

Abstract: An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion.

公开(公告)号：US09219487B1

公开(公告)日：2015-12-22

申请号：US14472431

申请日：2014-08-29

Applicant: Infineon Technologies AG

Inventor： Rainer Stuhlberger ,  Klemens Kordik

IPC: H03L7/197 ,  H03C3/09 ,  H03L7/085 ,  G01S13/88

CPC classification number: H03L7/1976 ,  G01S7/35 ,  G01S13/345 ,  G01S13/88 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/085 ,  H03L7/197 ,  H03L7/1974

Abstract: An RF transceiver circuit is disclosed herein. In accordance with one example of the disclosure the RF transceiver circuit includes a phase-locked-loop (PLL) with a fractional-N multi-modulus divider. The PLL operates in accordance with a PLL clock frequency and generates a frequency modulated RF output signal. The RF transceiver circuit further includes a modulator unit, which is configured to generate a sequence of division values dependent on a set of modulation parameters. The modulator operates in accordance with a system clock frequency, which is lower than the PLL clock frequency. A sample rate conversion unit is coupled between the modulator unit and a fractional-N multi-modulus divider. The sample rate conversion unit is configured to interpolate the sequence of division ratios to provide an interpolated sequence of division ratios at a rate corresponding to the PLL clock frequency.

Abstract translation: 本文公开了RF收发器电路。 根据本公开的一个示例，RF收发器电路包括具有分数N个多模式分频器的锁相环（PLL）。 PLL根据PLL时钟频率工作，并产生调频RF输出信号。 RF收发器电路还包括调制器单元，其被配置为生成依赖于一组调制参数的分频值序列。 调制器根据低于PLL时钟频率的系统时钟频率进行工作。 采样率转换单元耦合在调制器单元和分数N多模分频器之间。 采样率转换单元被配置为内插分频比序列，以对应于PLL时钟频率的速率提供分频比的内插序列。

公开(公告)号：US10970163B2

公开(公告)日：2021-04-06

申请号：US16577249

申请日：2019-09-20

Applicant: Infineon Technologies AG

Inventor： Bernhard Gstoettenbauer ,  Klemens Kordik

IPC: G06F11/10

Abstract: A frequency signal generator includes a controllable oscillator unit, a frequency control unit and an error detection unit. The controllable oscillator unit generates and provides a frequency signal. The frequency control unit generates a frequency control signal and the controllable oscillator unit varies a frequency of the frequency signal based on the frequency control signal. Further, the error detection unit receives the frequency control signal, detects an error within the frequency control signal and provides an error signal. The error signal comprises information on a detected error.

公开(公告)号：US09258000B1

公开(公告)日：2016-02-09

申请号：US14493539

申请日：2014-09-23

Applicant: Infineon Technologies AG

Inventor： Klemens Kordik ,  Thomas Sailer ,  Rainer Stuhlberger

IPC: H03L7/095

CPC classification number: H03L7/095 ,  H03L7/193

Abstract: A detector for detecting a locked state and an out-of-lock state of a phase locked loop includes an out-of-lock detector circuit that receives a reference signal and an input signal representing a PLL oscillator signal. The out-of-lock detector detects an out-of-lock state of the PLL and generates an out-of-lock signal indicating whether an out-of-lock state is detected. The detector further includes a lock detector circuit that receives the reference signal and the input signal, detects a locked state of the PLL, and generates a lock signal indicating whether a locked state is detected. A logic circuit receives both the out-of-lock signal and the lock signal and combines both signals to obtain an output signal indicative of whether the PLL is in a locked state or an out-of-lock state.

Abstract translation: 用于检测锁相环的锁定状态和失锁状态的检测器包括接收参考信号和表示PLL振荡器信号的输入信号的失锁检测器电路。 失锁检测器检测到PLL的失锁状态，并产生指示是否检测到失锁状态的失锁信号。 检测器还包括锁定检测器电路，其接收参考信号和输入信号，检测PLL的锁定状态，并产生指示是否检测到锁定状态的锁定信号。 逻辑电路接收失锁信号和锁定信号，并且组合两个信号以获得指示PLL是处于锁定状态还是处于非锁定状态的输出信号。

公开(公告)号：US20150007002A1

公开(公告)日：2015-01-01

申请号：US13930132

申请日：2013-06-28

Applicant: Infineon Technologies AG

Inventor： Bernhard Gstöttenbauer ,  Klemens Kordik

IPC: G06F11/07 ,  G06F11/10

CPC classification number: G06F11/1004

Abstract: A frequency signal generator includes a controllable oscillator unit, a frequency control unit and an error detection unit. The controllable oscillator unit generates and provides a frequency signal. The frequency control unit generates a frequency control signal and the controllable oscillator unit varies a frequency of the frequency signal based on the frequency control signal. Further, the error detection unit receives the frequency control signal, detects an error within the frequency control signal and provides an error signal. The error signal comprises information on a detected error.

Abstract translation: 频率信号发生器包括可控振荡器单元，频率控制单元和错误检测单元。 可控振荡器单元产生并提供频率信号。 频率控制单元产生频率控制信号，并且可控振荡器单元基于频率控制信号改变频率信号的频率。 此外，误差检测单元接收频率控制信号，检测频率控制信号内的误差并提供误差信号。 误差信号包括关于检测到的误差的信息。

公开(公告)号：US08908748B2

公开(公告)日：2014-12-09

申请号：US13651559

申请日：2012-10-15

Applicant: Infineon Technologies AG

Inventor： Klaus Buchner ,  Klemens Kordik ,  Christian Unhold

IPC: H04B1/38 ,  G06F13/40 ,  H04L29/10 ,  G11C16/10 ,  G06F13/42

CPC classification number: H04L29/10 ,  G06F13/4072 ,  G06F13/4291 ,  G11C16/10

Abstract: An interface circuit includes an interface terminal, a voltage detection device, an output driver and an enable logic. The interface terminal is configured to connect to an interface line. The voltage detection device is configured to detect a voltage present at the interface terminal. The output driver is configured to apply an output signal to the interface terminal. The enable logic is configured to generate an enable signal for the output driver based on an evaluation signal output by the voltage detection device, wherein the enable signal affects an enabling of the output driver if the evaluation signal shows that the voltage present at the interface terminal meets a given condition.

Abstract translation: 接口电路包括接口端子，电压检测装置，输出驱动器和使能逻辑。 接口终端配置为连接到接口线。 电压检测装置被配置为检测存在于接口端子处的电压。 输出驱动器被配置为向接口终端施加输出信号。 使能逻辑被配置为基于由电压检测装置输出的评估信号来产生用于输出驱动器的使能信号，其中如果评估信号示出存在于接口端子处的电压，则使能信号影响输出驱动器的使能 满足一定条件。

公开(公告)号：US20130094559A1

公开(公告)日：2013-04-18

申请号：US13651559

申请日：2012-10-15

Applicant: infineon Technologies AG

Inventor： Klaus Buchner ,  Klemens Kordik ,  Christian Unhold

IPC: H04B3/46 ,  H04B3/00

CPC classification number: H04L29/10 ,  G06F13/4072 ,  G06F13/4291 ,  G11C16/10

Abstract: An interface circuit includes an interface terminal, a voltage detection device, an output driver and an enable logic. The interface terminal is configured to connect to an interface line. The voltage detection device is configured to detect a voltage present at the interface terminal. The output driver is configured to apply an output signal to the interface terminal. The enable logic is configured to generate an enable signal for the output driver based on an evaluation signal output by the voltage detection device, wherein the enable signal affects an enabling of the output driver if the evaluation signal shows that the voltage present at the interface terminal meets a given condition.

Abstract translation: 接口电路包括接口端子，电压检测装置，输出驱动器和使能逻辑。 接口终端配置为连接到接口线。 电压检测装置被配置为检测存在于接口端子处的电压。 输出驱动器被配置为向接口终端施加输出信号。 使能逻辑被配置为基于由电压检测装置输出的评估信号来产生用于输出驱动器的使能信号，其中如果评估信号示出存在于接口端子处的电压，则使能信号影响输出驱动器的使能 满足一定条件。