公开(公告)号：US08908748B2

公开(公告)日：2014-12-09

申请号：US13651559

申请日：2012-10-15

Applicant: Infineon Technologies AG

Inventor： Klaus Buchner ,  Klemens Kordik ,  Christian Unhold

IPC: H04B1/38 ,  G06F13/40 ,  H04L29/10 ,  G11C16/10 ,  G06F13/42

CPC classification number: H04L29/10 ,  G06F13/4072 ,  G06F13/4291 ,  G11C16/10

Abstract: An interface circuit includes an interface terminal, a voltage detection device, an output driver and an enable logic. The interface terminal is configured to connect to an interface line. The voltage detection device is configured to detect a voltage present at the interface terminal. The output driver is configured to apply an output signal to the interface terminal. The enable logic is configured to generate an enable signal for the output driver based on an evaluation signal output by the voltage detection device, wherein the enable signal affects an enabling of the output driver if the evaluation signal shows that the voltage present at the interface terminal meets a given condition.

Abstract translation: 接口电路包括接口端子，电压检测装置，输出驱动器和使能逻辑。 接口终端配置为连接到接口线。 电压检测装置被配置为检测存在于接口端子处的电压。 输出驱动器被配置为向接口终端施加输出信号。 使能逻辑被配置为基于由电压检测装置输出的评估信号来产生用于输出驱动器的使能信号，其中如果评估信号示出存在于接口端子处的电压，则使能信号影响输出驱动器的使能 满足一定条件。

公开(公告)号：US20130094559A1

公开(公告)日：2013-04-18

申请号：US13651559

申请日：2012-10-15

Applicant: infineon Technologies AG

Inventor： Klaus Buchner ,  Klemens Kordik ,  Christian Unhold

IPC: H04B3/46 ,  H04B3/00

CPC classification number: H04L29/10 ,  G06F13/4072 ,  G06F13/4291 ,  G11C16/10

Abstract: An interface circuit includes an interface terminal, a voltage detection device, an output driver and an enable logic. The interface terminal is configured to connect to an interface line. The voltage detection device is configured to detect a voltage present at the interface terminal. The output driver is configured to apply an output signal to the interface terminal. The enable logic is configured to generate an enable signal for the output driver based on an evaluation signal output by the voltage detection device, wherein the enable signal affects an enabling of the output driver if the evaluation signal shows that the voltage present at the interface terminal meets a given condition.

Abstract translation: 接口电路包括接口端子，电压检测装置，输出驱动器和使能逻辑。 接口终端配置为连接到接口线。 电压检测装置被配置为检测存在于接口端子处的电压。 输出驱动器被配置为向接口终端施加输出信号。 使能逻辑被配置为基于由电压检测装置输出的评估信号来产生用于输出驱动器的使能信号，其中如果评估信号示出存在于接口端子处的电压，则使能信号影响输出驱动器的使能 满足一定条件。

公开(公告)号：US09385700B2

公开(公告)日：2016-07-05

申请号：US14497360

申请日：2014-09-26

Applicant: Infineon Technologies AG

Inventor： Klemens Kordik ,  Bernhard Gstoettenbauer ,  Klaus Buchner ,  Thomas Sailer

IPC: H03K5/24 ,  H03K4/08

CPC classification number: H03K5/24 ,  H03K4/08

Abstract: A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator and a comparator circuit. The pulse generator is configured to generate a sequence of pulses synchronous to the clock signal, wherein each pulse has an edge with a monotonously rising or falling signal level. The comparator circuit receives the sequence of pulses and is configured to detect, for each clock cycle of the clock signal, whether or not the signal level of the sequence of pulses is outside a desired range at a specific time instant within the clock cycle of the clock signal.

Abstract translation: 描述用于监视时钟信号的监视电路。 根据本公开的一个示例，监视电路包括脉冲发生器和比较器电路。 脉冲发生器被配置为产生与时钟信号同步的脉冲序列，其中每个脉冲具有单调上升或下降信号电平的边沿。 比较器电路接收脉冲序列，并被配置为在时钟信号的每个时钟周期内检测脉冲序列的信号电平是否在该时钟周期内的特定时刻在期望范围之外 时钟信号。

公开(公告)号：US20160094212A1

公开(公告)日：2016-03-31

申请号：US14497360

申请日：2014-09-26

Applicant: Infineon Technologies AG

Inventor： Klemens Kordik ,  Bernhard Gstoettenbauer ,  Klaus Buchner ,  Thomas Sailer

IPC: H03K5/24 ,  H03K4/08

CPC classification number: H03K5/24 ,  H03K4/08

Abstract: A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator and a comparator circuit. The pulse generator is configured to generate a sequence of pulses synchronous to the clock signal, wherein each pulse has an edge with a monotonously rising or falling signal level. The comparator circuit receives the sequence of pulses and is configured to detect, for each clock cycle of the clock signal, whether or not the signal level of the sequence of pulses is outside a desired range at a specific time instant within the clock cycle of the clock signal.

Abstract translation: 描述用于监视时钟信号的监视电路。 根据本公开的一个示例，监视电路包括脉冲发生器和比较器电路。 脉冲发生器被配置为产生与时钟信号同步的脉冲序列，其中每个脉冲具有单调上升或下降信号电平的边沿。 比较器电路接收脉冲序列，并且被配置为在时钟信号的每个时钟周期内检测脉冲序列的信号电平是否在该时钟周期内的特定时刻在期望范围之外 时钟信号。