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    Combined lock/out-of-lock detector for phase locked loops
    2.
    发明授权
    Combined lock/out-of-lock detector for phase locked loops 有权
    用于锁相环的组合锁/失锁检测器

    公开(公告)号：US09258000B1

    公开(公告)日：2016-02-09

    申请号：US14493539

    申请日：2014-09-23

    Applicant: Infineon Technologies AG

    Inventor： Klemens Kordik ,  Thomas Sailer ,  Rainer Stuhlberger

    IPC: H03L7/095

    CPC classification number: H03L7/095 ,  H03L7/193

    Abstract: A detector for detecting a locked state and an out-of-lock state of a phase locked loop includes an out-of-lock detector circuit that receives a reference signal and an input signal representing a PLL oscillator signal. The out-of-lock detector detects an out-of-lock state of the PLL and generates an out-of-lock signal indicating whether an out-of-lock state is detected. The detector further includes a lock detector circuit that receives the reference signal and the input signal, detects a locked state of the PLL, and generates a lock signal indicating whether a locked state is detected. A logic circuit receives both the out-of-lock signal and the lock signal and combines both signals to obtain an output signal indicative of whether the PLL is in a locked state or an out-of-lock state.

    Abstract translation: 用于检测锁相环的锁定状态和失锁状态的检测器包括接收参考信号和表示PLL振荡器信号的输入信号的失锁检测器电路。 失锁检测器检测到PLL的失锁状态，并产生指示是否检测到失锁状态的失锁信号。 检测器还包括锁定检测器电路，其接收参考信号和输入信号，检测PLL的锁定状态，并产生指示是否检测到锁定状态的锁定信号。 逻辑电路接收失锁信号和锁定信号，并且组合两个信号以获得指示PLL是处于锁定状态还是处于非锁定状态的输出信号。

    Radar front-end with RF oscillator monitoring
    3.
    发明授权
    Radar front-end with RF oscillator monitoring 有权

    公开(公告)号：US11137489B2

    公开(公告)日：2021-10-05

    申请号：US16870227

    申请日：2020-05-08

    Applicant: Infineon Technologies AG

    Inventor： Florian Starzer ,  Helmut Kollmann ,  Alexander Melzer ,  Rainer Stuhlberger ,  Roland Vuketich ,  Mathias Zinnoecker

    IPC: G01S13/34 ,  G01S7/35 ,  G01S13/87 ,  G01S13/931 ,  G01S7/40 ,  G01S7/03 ,  G01S13/42

    Abstract: A radar system includes a first chip having a first radio frequency (RF) contact; a second chip having a second RF contact; a first RF oscillator integrated in the first chip and has an output coupled to the first RF contact; a second RF oscillator integrated in the second chip; a transmission line connecting the first RF contact to the second RF contact; a demodulator that is arranged in the second chip and has a first RF input; wherein the first RF oscillator is configured to generate a first RF oscillator signal that is transmitted to the first RF input of the demodulator via the first RF contact, the transmission line, and the second RF contact, and wherein a controller is configured to determine a first propagation delay of the first RF oscillator signal arriving at the second chip on a basis of information obtained from the demodulator.

    Bandwidth adjustment in a phase-locked loop of a local oscillator
    4.
    发明授权
    Bandwidth adjustment in a phase-locked loop of a local oscillator 有权

    公开(公告)号：US10763783B2

    公开(公告)日：2020-09-01

    申请号：US16378046

    申请日：2019-04-08

    Applicant: Infineon Technologies AG

    Inventor： Lukas Heschl ,  Rainer Stuhlberger

    IPC: H03B5/12 ,  H03L7/08 ,  H03L7/099 ,  H03L7/089 ,  H03L7/189

    Abstract: A method for a radar device is described. According to one example implementation, the method comprises generating an RF signal using a voltage-controlled oscillator (VCO), wherein the frequency of the RF signal depends on a first tuning voltage and a second tuning voltage. The method also comprises setting the second tuning voltage using a phase-locked loop coupled to the VCO, with the result that the frequency of the RF signal corresponds to a desired frequency. The first tuning voltage is changed in such a manner that the second tuning voltage set by the phase-locked loop corresponds approximately to a predefined value. Another example implementation relates to a method for a radar device comprising: generating an RF signal using a VCO, wherein the frequency of the RF signal depends on a tuning voltage, setting the tuning voltage using a phase-locked loop coupled to the VCO, with the result that the frequency of the RF signal corresponds to a desired frequency, and determining a differential VCO gain of the VCO. The bandwidth of the phase-locked loop is set on the basis of the determined VCO gain.

    BANDWIDTH ADJUSTMENT IN A PHASE-LOCKED LOOP OF A LOCAL OSCILLATOR
    5.
    发明申请
    BANDWIDTH ADJUSTMENT IN A PHASE-LOCKED LOOP OF A LOCAL OSCILLATOR 审中-公开

    公开(公告)号：US20190319582A1

    公开(公告)日：2019-10-17

    申请号：US16378046

    申请日：2019-04-08

    Applicant: Infineon Technologies AG

    Inventor： Lukas HESCHL ,  Rainer Stuhlberger

    IPC: H03B5/12 ,  H03L7/08 ,  H03L7/099 ,  H03L7/189 ,  H03L7/089

    Abstract: A method for a radar device is described. According to one example implementation, the method comprises generating an RF signal using a voltage-controlled oscillator (VCO), wherein the frequency of the RF signal depends on a first tuning voltage and a second tuning voltage. The method also comprises setting the second tuning voltage using a phase-locked loop coupled to the VCO, with the result that the frequency of the RF signal corresponds to a desired frequency. The first tuning voltage is changed in such a manner that the second tuning voltage set by the phase-locked loop corresponds approximately to a predefined value. Another example implementation relates to a method for a radar device comprising: generating an RF signal using a VCO, wherein the frequency of the RF signal depends on a tuning voltage, setting the tuning voltage using a phase-locked loop coupled to the VCO, with the result that the frequency of the RF signal corresponds to a desired frequency, and determining a differential VCO gain of the VCO. The bandwidth of the phase-locked loop is set on the basis of the determined VCO gain.

    Generation of fast frequency ramps
    6.
    发明授权
    Generation of fast frequency ramps 有权

    公开(公告)号：US10320402B2

    公开(公告)日：2019-06-11

    申请号：US15843589

    申请日：2017-12-15

    Applicant: Infineon Technologies AG

    Inventor： Rainer Stuhlberger ,  Lukas Heschl

    IPC: H03L7/099 ,  H03L7/14 ,  H03G3/30 ,  H03L7/081 ,  H03L7/10 ,  G01S7/35 ,  G01S13/34 ,  G01S13/93

    Abstract: A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.

    RF receiver with testing capability
    7.
    发明授权
    RF receiver with testing capability 有权

    公开(公告)号：US09331797B2

    公开(公告)日：2016-05-03

    申请号：US14493610

    申请日：2014-09-23

    Applicant: Infineon Technologies AG

    Inventor： Klemens Kordik ,  Rainer Stuhlberger

    IPC: H04B17/00 ,  H04B17/29 ,  H04B17/23

    CPC classification number: H04B17/0085 ,  H04B17/14 ,  H04B17/17 ,  H04B17/23 ,  H04B17/29 ,  H04L7/0054

    Abstract: An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion.

    Radar transceiver with phase noise cancellation
    10.
    发明授权
    Radar transceiver with phase noise cancellation 有权

    公开(公告)号：US10663559B2

    公开(公告)日：2020-05-26

    申请号：US15726433

    申请日：2017-10-06

    Applicant: Infineon Technologies AG

    Inventor： Mario Huemer ,  Alexander Melzer ,  Alexander Onic ,  Rainer Stuhlberger

    IPC: G01S7/28 ,  G01S13/34 ,  G01S7/03 ,  G01S7/35 ,  G01S7/40 ,  H03B1/04 ,  G01S13/931 ,  G01S7/02

    Abstract: A method for cancelling phase noise in a radar signal is described herein. In accordance with one embodiment, the method includes transmitting an RF oscillator signal, which represents a local oscillator signal including phase noise, to a radar channel and receiving a respective first RF radar signal from the radar channel. The first RF radar signal included at least one radar echo of the transmitted RF oscillator signal. Further, the method includes applying the RF oscillator signal to an artificial radar target composed of circuitry, which applies a delay and a gain to the RF oscillator signal, to generate a second RF radar signal. The second RF radar signal is modulated by a modulation signal thus generating a frequency-shifted RF radar signal. Further, the method includes subtracting the frequency-shifted RF radar signal from the first RF radar signal.

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