公开(公告)号：US11127813B2

公开(公告)日：2021-09-21

申请号：US16617548

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin

IPC: H01L23/00 ,  H01L21/00 ,  H01L49/02 ,  H01F17/04 ,  H01L21/02 ,  H01L21/56 ,  H01L23/64

Abstract: The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.

公开(公告)号：US11374323B2

公开(公告)日：2022-06-28

申请号：US16473566

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Sonja Koller ,  Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Stephan Stoeckl ,  Thomas Wagner ,  Josef Hagn

IPC: H01Q9/04 ,  H01L23/00 ,  H01Q1/22 ,  H01Q21/06

Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.

公开(公告)号：US10403602B2

公开(公告)日：2019-09-03

申请号：US15637935

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L21/48 ,  H01L25/065 ,  H01L23/48 ,  G06F15/76 ,  H01L25/00

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.