公开(公告)号：US11784143B2

公开(公告)日：2023-10-10

申请号：US16421315

申请日：2019-05-23

Applicant: Intel Corporation

Inventor： Sonja Koller ,  Kilian Roth ,  Josef Hagn ,  Andreas Wolter ,  Andreas Augustin

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L21/48 ,  H01P3/00 ,  H01P11/00 ,  H01Q1/22 ,  H01L21/56

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/315 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/552 ,  H01P3/003 ,  H01P11/001 ,  H01Q1/2283 ,  H01L2223/6627 ,  H01L2223/6638 ,  H01L2223/6677

Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects. The first interconnects may include through-mold vias (TMVs), through-silicon vias (TSVs), conductive sidewalls, or conductive trenches.

公开(公告)号：US20190238163A1

公开(公告)日：2019-08-01

申请号：US16037241

申请日：2018-07-17

Applicant: Intel Corporation

Inventor： Shilpa Talwar ,  Christian Drewes ,  Andreas Augustin ,  Peter Noest ,  Stefan Mueller-Weinfurtner ,  Oner Orhan ,  Hosein Nikopour ,  Junyoung Nam

IPC: H04B1/00 ,  H04L27/26 ,  H03M7/30 ,  H04L25/03

Abstract: This disclosure relates to a data processing device, comprising: a digital front end (DFE) configured to convert an antenna signal to digital data, wherein the digital data comprises a plurality of data symbols; a baseband (BB) circuitry configured to process the digital data in baseband; and a digital interface between the DFE and the BB circuitry, wherein the DFE comprises a data compression circuitry configured to compress the plurality of data symbols for use in transmission via the digital interface to the BB circuitry.

公开(公告)号：US12191571B2

公开(公告)日：2025-01-07

申请号：US17323278

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Saravana Maruthamuthu ,  Bernd Waidhas ,  Andreas Augustin ,  Georg Seidemann

IPC: H01Q19/06 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/66 ,  H01Q1/48 ,  H01Q15/08

Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

公开(公告)号：US11764187B2

公开(公告)日：2023-09-19

申请号：US16641241

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin ,  Sonja Koller ,  Thomas Ort ,  Reinhard Mahnkopf

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

公开(公告)号：US11521793B2

公开(公告)日：2022-12-06

申请号：US17122351

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Saravana Maruthamuthu ,  Andreas Augustin ,  Andreas Wolter

IPC: H01F27/28 ,  H01F27/40 ,  H01G4/30 ,  H01G4/005 ,  H01G4/40 ,  H01F41/04 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H03B5/08 ,  H01L21/02 ,  H01L21/311 ,  H01L21/288 ,  H01L21/768

Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

公开(公告)号：US20220294115A1

公开(公告)日：2022-09-15

申请号：US17831151

申请日：2022-06-02

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Sonja Koller ,  Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Stephan Stoecki ,  Thomas Wagner ,  Josef Hagn

IPC: H01Q9/04 ,  H01L23/00 ,  H01Q1/22 ,  H01Q21/06

Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.

公开(公告)号：US10560125B2

公开(公告)日：2020-02-11

申请号：US16037241

申请日：2018-07-17

Applicant: Intel Corporation

Inventor： Shilpa Talwar ,  Christian Drewes ,  Andreas Augustin ,  Peter Noest ,  Stefan Mueller-Weinfurtner ,  Oner Orhan ,  Hosein Nikopour ,  Junyoung Nam

IPC: H04B1/00 ,  H04L27/26 ,  H04L25/03 ,  H03M7/30 ,  H04W28/06

Abstract: This disclosure relates to a data processing device, comprising: a digital front end (DFE) configured to convert an antenna signal to digital data, wherein the digital data comprises a plurality of data symbols; a baseband (BB) circuitry configured to process the digital data in baseband; and a digital interface between the DFE and the BB circuitry, wherein the DFE comprises a data compression circuitry configured to compress the plurality of data symbols for use in transmission via the digital interface to the BB circuitry.

公开(公告)号：US20190006318A1

公开(公告)日：2019-01-03

申请号：US15637935

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G06F15/76 ,  H01L21/486 ,  H01L23/481 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1011 ,  H01L2225/1017 ,  H01L2225/1058

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US11646498B2

公开(公告)日：2023-05-09

申请号：US16414356

申请日：2019-05-16

Applicant: Intel Corporation

Inventor： Kilian Roth ,  Sonja Koller ,  Josef Hagn ,  Andreas Wolter ,  Andreas Augustin

IPC: H01L23/34 ,  H01Q13/18 ,  H01L23/66 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01Q1/22

CPC classification number: H01Q13/18 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/528 ,  H01L23/66 ,  H01Q1/2283 ,  H01L2223/6616 ,  H01L2223/6677

Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a cavity resonator antenna over the first conductive layer and substrate. The cavity resonator antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the cavity resonator antenna, first conductive layer, and substrate. The conductive cavity may extend vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects. The first interconnects may include through-mold vias (TMVs), through-silicon vias (TSVs), conductive sidewalls, or conductive trenches.

公开(公告)号：US11456116B2

公开(公告)日：2022-09-27

申请号：US16474015

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Bernd Waidhas ,  Sonja Koller ,  Reinhard Mahnkopf ,  Georg Seidemann

IPC: H01F27/24 ,  H01F41/04 ,  H01F17/00 ,  H01L23/64 ,  H01L27/01 ,  H01L49/02

Abstract: A recess in a die backside surface occupies a footprint that accommodates an inductor coil that is formed in metallization above an active surface of the die. Less semiconductive material is therefore close to the inductor coil. A ferromagnetic material is formed in the recess, or a ferromagnetic material is formed on a dielectric layer above the inductor coil. The recess may extend across a die that allows the die to be deflected at the recess.