公开(公告)号：US20210226917A1

公开(公告)日：2021-07-22

申请号：US17222962

申请日：2021-04-05

Applicant: Intel Corporation

Inventor： Vladimir MEDVEDKIN ,  Andrey CHILIKIN

IPC: H04L29/12

Abstract: Examples include a computing system having a plurality of processing cores and a memory coupled to the plurality of processing cores. The memory has instructions stored thereon that, in response to execution by a selected one of the plurality of processing cores, cause the following actions. The selected processing core to receive a packet and get an original tuple from the packet. When no state information for a packet flow of the packet exists in a state table, select a new network address as a new source address for the packet, get a reverse tuple for a reverse direction, select a port for the packet from an entry in a mapping table based on a hash procedure using the reverse tuple, and save the new network address and selected port. Translate the packet's network address and port and transmit the packet.

公开(公告)号：US20240334245A1

公开(公告)日：2024-10-03

申请号：US18737212

申请日：2024-06-07

Applicant: Intel Corporation

Inventor： John J. BROWNE ,  Andrey CHILIKIN ,  Elazar COHEN ,  Joseph HASTING ,  James CLEE ,  Jerry PIROG ,  Jamison D. WHITESELL ,  Ambalavanar ARULAMBALAM ,  Anjali Singhai JAIN ,  Andrew CUNNINGHAM ,  Ruben DAHAN

IPC: H04W28/06 ,  H04W28/02

CPC classification number: H04W28/06 ,  H04W28/0273 ,  H04W28/0289

Abstract: Examples described herein relate to a network interface device that performs: offloading processing of fragments of a packet to an accelerator; processing non-fragmented packets; and prioritizing dropping of fragments of the packet over dropping of non-fragmented packets. Offloading processing of fragments of the packet to the accelerator can include: the accelerator performing: reassembling the fragments of the packet into a first reassembly packet; and based on congestion associated with at least one of the fragments of the packet of the first reassembly packet: dropping fragments of the first reassembly packet associated with one or more flows; halting reassembly of the first reassembly packet; and forwarding a second packet to a host system, wherein the second packet indicates that congestion occurred, identifies one or more impacted flows, and indicates a number of dropped packet fragments.

公开(公告)号：US20210014324A1

公开(公告)日：2021-01-14

申请号：US17031659

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Andrey CHILIKIN ,  Tomasz KANTECKI ,  Chris MACNAMARA ,  John J. BROWNE ,  Declan DOHERTY ,  Niall POWER

IPC: H04L29/08 ,  H04L12/24 ,  H04L12/26 ,  G06F12/0862 ,  G06F1/28

Abstract: Examples described herein relate to a network interface apparatus that includes an interface; circuitry to determine whether to store content of a received packet into a cache or into a memory, at least during a configuration of the network interface to store content directly into the cache, based at least in part on a fill level of a region of the cache allocated to receive copies of packet content directly from the network interface; and circuitry to store content of the received packet into the cache or the memory based on the determination, wherein the cache is external to the network interface. In some examples, the network interface is to determine to store content of the received packet into the memory based at least in part on a fill level of the region of the cache being identified as full or determine to store content of the received packet into the cache based at least in part on a fill level of the region of the cache being identified as not filled. In some examples, the network interface is to indicate a complexity level of content of the received packet to cause adjustment of a power usage level of a processor that is to process the content of the received packet.

公开(公告)号：US20190334863A1

公开(公告)日：2019-10-31

申请号：US16394715

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Vladimir MEDVEDKIN ,  Andrey CHILIKIN

IPC: H04L29/12

Abstract: Examples include a computing system having a plurality of processing cores and a memory coupled to the plurality of processing cores. The memory has instructions stored thereon that, in response to execution by a selected one of the plurality of processing cores, cause the following actions. The selected processing core to receive a packet and get an original tuple from the packet. When no state information for a packet flow of the packet exists in a state table, select a new network address as a new source address for the packet, get a reverse tuple for a reverse direction, select a port for the packet from an entry in a mapping table based on a hash procedure using the reverse tuple, and save the new network address and selected port. Translate the packet's network address and port and transmit the packet.

公开(公告)号：US20190199613A1

公开(公告)日：2019-06-27

申请号：US16286179

申请日：2019-02-26

Applicant: Intel Corporation

Inventor： Krishnamurthy JAMBUR SATHYANARAYANA ,  Fiona TRAHE ,  Anthony KELLY ,  Brendan RYAN ,  Stephen DOYLE ,  Andrey CHILIKIN

IPC: H04L12/26 ,  H04L12/46

CPC classification number: H04L43/0876 ,  H04L12/4641 ,  H04L43/16

Abstract: Examples include techniques to monitor control plane (CP) network traffic. Examples include monitoring CP traffic between one or more user equipment (UEs) wirelessly coupled to a network and a virtual network function arranged to process user plane (UP) traffic for an application service provided to the one or more UEs to determine whether at least a portion of the UP traffic needs to be routed to a different VNF for UP processing.