公开(公告)号：US20230129107A1

公开(公告)日：2023-04-27

申请号：US18086030

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Iliya BOKHMAN ,  Elazar COHEN

IPC: G06F12/0891 ,  G06F12/0804

Abstract: A network device performs packet processing operations on packets received from a network and includes a write back cache to store data (for example, counters) used to perform the packet processing operations. The data stored in the write cache in the network device are evicted from the write back cache to an external memory from time to time using a write-back operation that includes a read-modify-write of a line in the external memory. Instead of performing a separate read-modify-write for each data stored in the cache line, a single read-modify-write operation is performed for all data stored in the cache line in the write back cache. The aggregation of relatively close data for the single read-modify-write operation reduces the number of memory accesses to the external memory and improves the bandwidth to the external memory.

公开(公告)号：US20210328929A1

公开(公告)日：2021-10-21

申请号：US17359539

申请日：2021-06-26

Applicant: Intel Corporation

Inventor： Boris KLEIMAN ,  Marina POPILOV ,  Anjali Singhai JAIN ,  Piotr UMINSKI ,  Elazar COHEN ,  Kirill KAZATSKER ,  Sarig LIVNE ,  Neerav PARIKH

IPC: H04L12/803 ,  H04L12/819 ,  H04L12/863 ,  H04L12/923 ,  H04L12/911

Abstract: Examples described herein relate to a network interface device that includes packet processing circuitry to detect usage of an egress port and report the usage of the egress port to a network interface device driver to cause reallocation of hash-based packet buckets to at least one egress port to provide an allocation of hash-based packet buckets to multiple active egress ports of the network interface device with retention of bucket-to-egress port mappings except for re-allocations of one or more buckets to one or more active egress ports. In some examples, usage of the egress port is based on a count of hash buckets assigned to packets to be transmitted from the egress port or a number of bytes of packets enqueued to be transmitted from the egress port.

公开(公告)号：US20240334245A1

公开(公告)日：2024-10-03

申请号：US18737212

申请日：2024-06-07

Applicant: Intel Corporation

Inventor： John J. BROWNE ,  Andrey CHILIKIN ,  Elazar COHEN ,  Joseph HASTING ,  James CLEE ,  Jerry PIROG ,  Jamison D. WHITESELL ,  Ambalavanar ARULAMBALAM ,  Anjali Singhai JAIN ,  Andrew CUNNINGHAM ,  Ruben DAHAN

IPC: H04W28/06 ,  H04W28/02

CPC classification number: H04W28/06 ,  H04W28/0273 ,  H04W28/0289

Abstract: Examples described herein relate to a network interface device that performs: offloading processing of fragments of a packet to an accelerator; processing non-fragmented packets; and prioritizing dropping of fragments of the packet over dropping of non-fragmented packets. Offloading processing of fragments of the packet to the accelerator can include: the accelerator performing: reassembling the fragments of the packet into a first reassembly packet; and based on congestion associated with at least one of the fragments of the packet of the first reassembly packet: dropping fragments of the first reassembly packet associated with one or more flows; halting reassembly of the first reassembly packet; and forwarding a second packet to a host system, wherein the second packet indicates that congestion occurred, identifies one or more impacted flows, and indicates a number of dropped packet fragments.

公开(公告)号：US20240031289A1

公开(公告)日：2024-01-25

申请号：US18375480

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Arunkumar BALAKRISHNAN ,  Anurag AGRAWAL ,  Elazar COHEN ,  Anjali Singhai JAIN

IPC: H04L45/748 ,  H04L45/00 ,  H04L12/46

CPC classification number: H04L45/748 ,  H04L45/566 ,  H04L12/4633

Abstract: Examples described herein relate to a network interface device. The network interface device can include circuitry that is to: perform a route lookup for a packet based on first and second lookup operations, wherein the first lookup operation comprises a longest prefix match (LPM) to output a route identifier based on a destination Internet Protocol (IP) address of the packet and wherein the second look up operation comprises an exact match operation to determine an action based on the route identifier and a packet header.

公开(公告)号：US20230055703A1

公开(公告)日：2023-02-23

申请号：US17983197

申请日：2022-11-08

Applicant: Intel Corporation

Inventor： Andrey CHILIKIN ,  Vladimir MEDVEDKIN ,  Elazar COHEN

IPC: H04L49/00 ,  H04L45/7453 ,  H04L49/9047

Abstract: An apparatus is described. The apparatus includes queue assignment circuitry. The queue assignment circuitry includes first circuitry to select amongst multiple hash keys and second circuitry to hash content of a packet's header with a selected one of the hash keys.

公开(公告)号：US20220385534A1

公开(公告)日：2022-12-01

申请号：US17882317

申请日：2022-08-05

Applicant: Intel Corporation

Inventor： Elazar COHEN ,  Keren GUY ,  Marina POPILOV ,  Andrey CHILIKIN

IPC: H04L41/08 ,  H04L41/0894 ,  H04L41/0816

Abstract: Examples described herein relate to a network interface device comprising circuitry and data plane circuitry. In some examples, the circuitry is to receive control configurations from multiple control planes and based on a management configuration, selectively deny a control configuration of the received control configurations to configure operations of the data plane circuitry. In some examples, selectively denying the control configuration comprises restrict different control planes from modification of configuration of the data plane circuitry