公开(公告)号：US20200066897A1

公开(公告)日：2020-02-27

申请号：US16318108

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Roman W. OLAC-VAW ,  Joodong PARK ,  Chen-Guan LEE ,  Chia-Hong JAN ,  Everett S. CASSIDY-COMFORT

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.

公开(公告)号：US20200066712A1

公开(公告)日：2020-02-27

申请号：US16318107

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Roman W. OLAC-VAW ,  Joodong PARK ,  Chen-Guan LEE ,  Chia-Hong JAN

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H01L21/8234

Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.

公开(公告)号：US20180114695A1

公开(公告)日：2018-04-26

申请号：US15573458

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Chen-Guan LEE ,  Lu YANG ,  Joodong PARK ,  Chia-Hong JAN

IPC: H01L21/225 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/2255 ,  H01L27/0886 ,  H01L29/0638 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/785

Abstract: Dual height glass is described for doping a fin of a field effect transistor structure in an integrated circuit. In one example, a method includes applying a glass layer over a fin of a FinFET structure, the fin having a source/drain region and a gate region, applying a polysilicon layer over the gate region, removing a portion of the glass layer from the source/drain region after applying the polysilicon, and thermally annealing the glass to drive dopants into the fin, and applying an epitaxial layer over the source/drain region.