公开(公告)号：US20190006362A1

公开(公告)日：2019-01-03

申请号：US16103430

申请日：2018-08-14

申请人： Intel Corporation

发明人： Tahir GHANI ,  Salman LATIF ,  Chanaka D. MUNASINGHE

IPC分类号： H01L27/092 ,  H01L29/08 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC分类号： H01L27/0924 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/31051 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66803

摘要： Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

公开(公告)号：US10056380B2

公开(公告)日：2018-08-21

申请号：US14779936

申请日：2013-06-20

申请人： Intel Corporation

发明人： Tahir Ghani ,  Salman Latif ,  Chanaka D. Munasinghe

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

CPC分类号： H01L27/0924 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/31051 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66803

摘要： Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

公开(公告)号：US20180175212A1

公开(公告)日：2018-06-21

申请号：US15895541

申请日：2018-02-13

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L21/225 ,  H01L29/423 ,  H01L21/324 ,  H01L29/51

CPC分类号： H01L29/78621 ,  H01L21/2252 ,  H01L21/2255 ,  H01L21/324 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642

摘要： A vertical transistor includes a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type. The proximate spacer is formed on an upper surface of a semiconductor substrate. At least one channel region extends vertically from the proximate doping source layer to the distal doping source layer. A proximate S/D extension region is adjacent the proximate spacer and a distal S/D extension region is adjacent the distal spacer. The proximate and distal S/D extension regions include dopants that match the first dopant-type of the proximate and distal doping sources.

公开(公告)号：US10002954B2

公开(公告)日：2018-06-19

申请号：US15100286

申请日：2014-01-24

申请人： Walid M. Hafez ,  Chia-Hong Jan

发明人： Walid M. Hafez ,  Chia-Hong Jan

IPC分类号： H01L29/66 ,  H01L29/74 ,  H01L29/417 ,  H01L29/06 ,  H01L27/02 ,  H01L21/225 ,  H01L29/78

CPC分类号： H01L29/74 ,  H01L21/2255 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/41716 ,  H01L29/66363 ,  H01L29/785

摘要： Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US09978649B2

公开(公告)日：2018-05-22

申请号：US15465311

申请日：2017-03-21

申请人： Tokyo Electron Limited

发明人： Robert D. Clark ,  Steven P. Consiglio ,  Jeffrey Smith

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L21/033 ,  H01L27/092 ,  H01L29/161 ,  H01L29/167

CPC分类号： H01L21/823814 ,  H01L21/0332 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/324 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： A method is provided for solid source doping for source and drain extensions. According to one embodiment, the method includes providing a substrate containing fins of first and second film stacks, sacrificial gates across and on the fins of the first and second film stacks, where the first and second film stacks include alternating first and second films, and where the first films extend through sidewall spacers on the sacrificial gates, selectively forming a first mask layer on the sidewall spacers and on the first films of the first film stack, depositing a first dopant layer on the substrate, heat-treating the substrate to diffuse dopants from the first dopant layer into the first films of the second film stack to form doped first films in the second film stack, and removing the first mask layer from the substrate. The processing steps may be repeated for the second film stack.

公开(公告)号：US20180082843A1

公开(公告)日：2018-03-22

申请号：US15463446

申请日：2017-03-20

申请人： TOSHIBA MEMORY CORPORATION

发明人： Tatsunori ISOGAI

IPC分类号： H01L21/225 ,  H01L27/12 ,  H01L29/786 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/10 ,  H01L21/324 ,  H01L21/02 ,  H01L21/28

CPC分类号： H01L21/2255 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/324 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/124 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/78675 ,  H01L29/78696

摘要： In a manufacturing method of a semiconductor device according to an embodiment, an oxide film is formed on a semiconductor layer containing an impurity. A heat treatment is performed on the semiconductor layer to diffuse part of the impurity into the oxide film with hydrogen plasma treatment on the oxide film or with ultraviolet irradiation on the oxide film. After the heat treatment, the oxide film is removed.

公开(公告)号：US20180076200A1

公开(公告)日：2018-03-15

申请号：US15463821

申请日：2017-03-20

申请人： International Business Machines Corporation

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/2255 ,  H01L21/3081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/7851

摘要： An advanced FinFET structure is described. A FinFET device includes a set of n-type FinFET devices and a set of p-type FinFET devices disposed on a substrate. The set of n-type FinFET devices have silicon channels and the set of p-type FinFET devices have silicon germanium channels. A set of punchthrough stop isolation regions are disposed under and isolate the n-type FinFET devices. A set of oxide isolation regions are disposed under and isolate the set of p-type FinFET devices.

公开(公告)号：US09917163B2

公开(公告)日：2018-03-13

申请号：US15437932

申请日：2017-02-21

申请人： Infineon Technologies AG

发明人： Andreas Meiser ,  Till Schloesser

IPC分类号： H01L29/78 ,  H01L27/15 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40

CPC分类号： H01L29/4175 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/156 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835

摘要： A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.

公开(公告)号：US20180033625A1

公开(公告)日：2018-02-01

申请号：US15662107

申请日：2017-07-27

申请人： ASM IP Holding B.V.

发明人： Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim

IPC分类号： H01L21/225 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/3065

CPC分类号： H01L21/225 ,  H01L21/2255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31053

摘要： A method of processing a substrate to enable selective doping without a photolithography process is provided. The method includes forming a diffusion barrier on the substrate having a patterned structure using plasma deposition method, removing the diffusion barrier except for part of the diffusion barrier using wet etching, forming a diffusion source layer on the patterned structure and the part of the diffusion barrier, and applying energy to the diffusion source layer.

公开(公告)号：US09881919B2

公开(公告)日：2018-01-30

申请号：US15059516

申请日：2016-03-03

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Effendi Leobandung ,  Tenko Yamashita

IPC分类号： H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L31/0288 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8238

CPC分类号： H01L21/2257 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/0638 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/66537 ,  H01L29/66803

摘要： A method for doping fins includes depositing a first dopant layer at a base of fins formed in a substrate, depositing a dielectric layer on the first dopant layer and etching the dielectric layer and the first dopant layer in a first region to expose the substrate and the fins. A second dopant layer is conformally deposited over the fins and the substrate in the first region. The second dopant layer is recessed to a height on the fins in the first region. An anneal is performed to drive dopants into the fins from the first dopant layer in a second region and from the second dopant layer in the first region to concurrently form punch through stoppers in the fins and wells in the substrate.