DEPLETION MODE GATE IN ULTRATHIN FINFET BASED ARCHITECTURE

    公开(公告)号:US20200066907A1

    公开(公告)日:2020-02-27

    申请号:US16317708

    申请日:2016-09-30

    Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.

    ULTRA-SCALED FIN PITCH PROCESSES HAVING DUAL GATE DIELECTRICS AND THE RESULTING STRUCTURES

    公开(公告)号:US20200066897A1

    公开(公告)日:2020-02-27

    申请号:US16318108

    申请日:2016-09-30

    Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.

    METAL RESISTOR AND SELF-ALIGNED GATE EDGE (SAGE) ARCHITECTURE HAVING A METAL RESISTOR

    公开(公告)号:US20200066712A1

    公开(公告)日:2020-02-27

    申请号:US16318107

    申请日:2016-09-29

    Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.

    TRANSMISSION LINES USING BENDING FINS FROM LOCAL STRESS

    公开(公告)号:US20190278022A1

    公开(公告)日:2019-09-12

    申请号:US16462077

    申请日:2016-12-30

    Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.

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