-
公开(公告)号：US12087491B2
公开(公告)日：2024-09-10
申请号：US18200062
申请日：2023-05-22
Applicant: Intel Corporation
Inventor： Chuanzhao Yu , Qiang Li , David Newman
CPC classification number: H01F27/2804 , H01F41/041 , H01F2027/2809
Abstract: An inductance apparatus includes a first winding comprising a first wire section and a second wire section. The first wire section and the second wire section are disposed in a first horizontal plane associated with a center axis, and the first winding is associated with an equivalent current flow path within the first horizontal plane; a second winding extends via the center axis in the first horizontal plane to the first wire section and the second wire section, wherein the equivalent current flow path of the first winding is aligned with a current flow path associated with the second winding.
-
公开(公告)号：US20220038069A1
公开(公告)日：2022-02-03
申请号：US17405780
申请日：2021-08-18
Applicant: Intel Corporation
Inventor： Kaushik Dasgupta , Chuanzhao Yu , Chintan Thakkar , Saeid Daneshgar , Hyun Yoon , Xi Li , Anandaroop Chakrabarti , Stefan Shopov
Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.
-
公开(公告)号：US20210313943A1
公开(公告)日：2021-10-07
申请号：US17315931
申请日：2021-05-10
Applicant: Intel Corporation
Inventor： Kaushik Dasgupta , Chuanzhao Yu , Chintan Thakkar , SAEID DANESHGAR , Hyun Yoon , Xi Li , Anandaroop Chakrabarti , Stefan Shopov
Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.
-
-
Search Results
13
records
(took 0.015 seconds)
