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公开(公告)号：US11694836B2
公开(公告)日：2023-07-04
申请号：US16958049
申请日：2018-03-30
Applicant: Intel Corporation
Inventor： Chuanzhao Yu , Qiang Li , David Newman
CPC classification number: H01F27/2804 , H01F41/041 , H01F2027/2809
Abstract: A stacked transformer or inductor apparatus including a first layer with a first layer wire element extending around a center axis and a second layer with a second layer wire element. The second layer element includes side by side first and second wire components in parallel spaced relation extending around the center axis and the first wire component is connected to the first layer wire element to form a primary turn winding. A third layer includes a third layer wire element extending around the center axis and connected to the second wire component of the second layer wire element to form a secondary turn winding partially overlapping with the primary turn winding.
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公开(公告)号：US20230198479A1
公开(公告)日：2023-06-22
申请号：US17559341
申请日：2021-12-22
Applicant: Intel Corporation
Inventor： Muhammed Elgousi , Chuanzhao Yu , Hyun Yoon , Xi Li , LiChung Tony Chang
CPC classification number: H03F3/21 , H03F3/005 , H03F1/26 , H03F2200/372
Abstract: A method for harmonic trapping in a matching network of a power amplifier includes determining primary inductance and secondary inductance of a differential transformer of the matching network, based on a signal operating frequency of the power amplifier. An inductance value for an L-C filter is determined based on the secondary inductance and a harmonic frequency of a local oscillator (LO) signal. A capacitance value for the L-C filter is determined based on the inductance value and the harmonic frequency of the LO signal. The L-C filter is provided on an electric connection between a direct current (DC) bias voltage source and a secondary inductor of the differential transformer. The L-C filter is configured with the determined inductance value and the determined capacitance value.
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公开(公告)号：US20220166430A1
公开(公告)日：2022-05-26
申请号：US17669762
申请日：2022-02-11
Applicant: Intel Corporation
Inventor： Chuanzhao Yu , Stephan Leuschner , David Newman
IPC: H03K17/693 , H03H7/42 , H03K17/06 , H03K17/16
Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.
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公开(公告)号：US11075779B2
公开(公告)日：2021-07-27
申请号：US16958123
申请日：2018-03-30
Applicant: Intel Corporation
Inventor： Chuanzhao Yu , Hyun Yoon , Kurt Hausmann
IPC: H04L25/02 , H03K19/0185 , H04L27/20
Abstract: A buffer circuit includes a first feedback buffer to receive a first component of a current-mode signal and a second feedback buffer to receive a second component of the current-mode signal. The buffer circuit also including a first inverter having a first input coupled to an output of the second feedback buffer and to an input of a first current circuit through a first filter, a first output coupled to an input of the first feedback buffer. The buffer circuit also includes a second inverter having a second input coupled to an output of the first feedback buffer and to an input of a second current circuit through a second filter, and a second output coupled to an input of the second feedback buffer.
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公开(公告)号：US11632108B2
公开(公告)日：2023-04-18
申请号：US17669762
申请日：2022-02-11
Applicant: Intel Corporation
Inventor： Chuanzhao Yu , Stephan Leuschner , David Newman
IPC: H03K17/693 , H03H7/42 , H03K17/06 , H03K17/16
Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.
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Patent Agency Ranking
公开(公告)号：US11283444B2
公开(公告)日：2022-03-22
申请号：US16766843
申请日：2018-03-28
Applicant: Intel Corporation
Inventor： Chuanzhao Yu , Stephan Leuschner , David Newman
IPC: H03K17/693 , H03H7/42 , H03K17/06 , H03K17/16
Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.
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公开(公告)号：US12237816B2
公开(公告)日：2025-02-25
申请号：US17405780
申请日：2021-08-18
Applicant: Intel Corporation
Inventor： Kaushik Dasgupta , Chuanzhao Yu , Chintan Thakkar , Saeid Daneshgar , Hyun Yoon , Xi Li , Anandaroop Chakrabarti , Stefan Shopov
Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.
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公开(公告)号：US20240029942A1
公开(公告)日：2024-01-25
申请号：US18200062
申请日：2023-05-22
Applicant: Intel corporation
Inventor： Chuanzhao Yu , Qiang Li , David Newman
CPC classification number: H01F27/2804 , H01F41/041 , H01F2027/2809
Abstract: A stacked transformer or inductor apparatus including a first layer with a first layer wire element extending around a center axis and a second layer with a second layer wire element. The second layer element includes side by side first and second wire sections in parallel spaced relation extending around the center axis and the first wire section is connected to the first layer wire element to form a primary turn winding. A third layer includes a third layer wire element extending around the center axis and connected to the second wire section of the second layer wire element to form a secondary turn winding partially overlapping with the primary turn winding.
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公开(公告)号：US11632092B2
公开(公告)日：2023-04-18
申请号：US17315931
申请日：2021-05-10
Applicant: Intel Corporation
Inventor： Kaushik Dasgupta , Chuanzhao Yu , Chintan Thakkar , Saeid Daneshgar , Hyun Yoon , Xi Li , Anandaroop Chakrabarti , Stefan Shopov
Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.
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公开(公告)号：US11031918B2
公开(公告)日：2021-06-08
申请号：US16177790
申请日：2018-11-01
Applicant: Intel Corporation
Inventor： Kaushik Dasgupta , Chuanzhao Yu , Chintan Thakkar , Saeid Daneshgar , Hyun Yoon , Xi Li , Anandaroop Chakrabarti , Stefan Shopov
Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.
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