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公开(公告)号：US20230198479A1
公开(公告)日：2023-06-22
申请号：US17559341
申请日：2021-12-22
Applicant: Intel Corporation
Inventor： Muhammed Elgousi , Chuanzhao Yu , Hyun Yoon , Xi Li , LiChung Tony Chang
CPC classification number: H03F3/21 , H03F3/005 , H03F1/26 , H03F2200/372
Abstract: A method for harmonic trapping in a matching network of a power amplifier includes determining primary inductance and secondary inductance of a differential transformer of the matching network, based on a signal operating frequency of the power amplifier. An inductance value for an L-C filter is determined based on the secondary inductance and a harmonic frequency of a local oscillator (LO) signal. A capacitance value for the L-C filter is determined based on the inductance value and the harmonic frequency of the LO signal. The L-C filter is provided on an electric connection between a direct current (DC) bias voltage source and a secondary inductor of the differential transformer. The L-C filter is configured with the determined inductance value and the determined capacitance value.
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公开(公告)号：US20230188194A1
公开(公告)日：2023-06-15
申请号：US17550629
申请日：2021-12-14
Applicant: Intel Corporation
Inventor： Bruce Geren , Wayne Ballantyne , Gregory Chance , Xi Li , Peter Pawliuk , Nebil Tanzi
CPC classification number: H04B7/0695 , H04B7/15507 , H04W76/14 , H04W76/32
Abstract: A wireless communication device can include modem circuitry to connect the UE to a repeater over a side-link connection. The device can also include processing circuitry to control a repeater beamforming process to select a beam angle from the repeater to a base station and initiate a communication procedure using the selected beam angle. Other methods, systems and apparatuses are described.
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Patent Agency Ranking
公开(公告)号：US12237816B2
公开(公告)日：2025-02-25
申请号：US17405780
申请日：2021-08-18
Applicant: Intel Corporation
Inventor： Kaushik Dasgupta , Chuanzhao Yu , Chintan Thakkar , Saeid Daneshgar , Hyun Yoon , Xi Li , Anandaroop Chakrabarti , Stefan Shopov
Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.
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公开(公告)号：US11632092B2
公开(公告)日：2023-04-18
申请号：US17315931
申请日：2021-05-10
Applicant: Intel Corporation
Inventor： Kaushik Dasgupta , Chuanzhao Yu , Chintan Thakkar , Saeid Daneshgar , Hyun Yoon , Xi Li , Anandaroop Chakrabarti , Stefan Shopov
Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.
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公开(公告)号：US11031918B2
公开(公告)日：2021-06-08
申请号：US16177790
申请日：2018-11-01
Applicant: Intel Corporation
Inventor： Kaushik Dasgupta , Chuanzhao Yu , Chintan Thakkar , Saeid Daneshgar , Hyun Yoon , Xi Li , Anandaroop Chakrabarti , Stefan Shopov
Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.
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公开(公告)号：US20220038069A1
公开(公告)日：2022-02-03
申请号：US17405780
申请日：2021-08-18
Applicant: Intel Corporation
Inventor： Kaushik Dasgupta , Chuanzhao Yu , Chintan Thakkar , Saeid Daneshgar , Hyun Yoon , Xi Li , Anandaroop Chakrabarti , Stefan Shopov
Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.
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公开(公告)号：US20210313943A1
公开(公告)日：2021-10-07
申请号：US17315931
申请日：2021-05-10
Applicant: Intel Corporation
Inventor： Kaushik Dasgupta , Chuanzhao Yu , Chintan Thakkar , SAEID DANESHGAR , Hyun Yoon , Xi Li , Anandaroop Chakrabarti , Stefan Shopov
Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.
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