公开(公告)号：US20240395696A1

公开(公告)日：2024-11-28

申请号：US18797197

申请日：2024-08-07

Applicant: Intel Corporation

Inventor： Aaron J. WELSH ,  Christopher M. PELTO ,  David J. TOWNER ,  Mark A. BLOUNT ,  Takayoshi ITO ,  Dragos SEGHETE ,  Christopher R. RYDER ,  Stephanie F. SUNDHOLM ,  Chamara ABEYSEKERA ,  Anil W. DEY ,  Che-Yun LIN ,  Uygar E. AVCI

IPC: H01L23/522

Abstract: Metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.

公开(公告)号：US20220416039A1

公开(公告)日：2022-12-29

申请号：US17357711

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  David J. TOWNER ,  Orb ACTON ,  Jitendra Kumar JHA ,  YenTing CHIU ,  Mohit K. HARAN ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L29/49

Abstract: An integrated circuit structure comprises a first and second vertical arrangement of horizontal nanowires in a PMOS region and in an NMOS region. A first gate stack having a P-type conductive layer surrounds the first vertical arrangement of horizontal nanowires. A second gate stack surrounds the second vertical arrangement of horizontal nanowires. In one embodiment, the second gate stack has an N-type conductive layer, the P-type conductive layer is over the second gate stack, and an N-type conductive fill is between N-type conductive layer and the P-type conductive layer to provide same polarity metal filled gates. In another embodiment, the second gate stack has an N-type conductive layer comprising Titanium (Ti) and “Nitrogen (N) having a low saturation thickness of 3-3.5 nm surrounding the nanowires, and the N-type conductive layer is covered by the P-type conductive layer.

公开(公告)号：US20220068794A1

公开(公告)日：2022-03-03

申请号：US17129858

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Aaron J. WELSH ,  Christopher M. PELTO ,  David J. TOWNER ,  Mark A. BLOUNT ,  Takayoshi ITO ,  Dragos SEGHETE ,  Christopher R. RYDER ,  Stephanie F. SUNDHOLM ,  Chamara ABEYSEKERA ,  Anil W. DEY ,  Che-Yun LIN ,  Uygar E. AVCI

IPC: H01L23/522 ,  H01L49/02

Abstract: Metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.