公开(公告)号：US20230290852A1

公开(公告)日：2023-09-14

申请号：US17694170

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  YenTing CHIU ,  David J. TOWNER ,  David N. GOLDSTEIN ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/785

Abstract: Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with differentiated dipole layers are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a mid-gap to P-type conductive layer over a first gate dielectric including a high-k dielectric layer and a first dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having the mid-gap to P-type conductive layer over a second gate dielectric including the high-k dielectric layer and a second dipole material layer, the second dipole layer different than the first dipole material layer.

公开(公告)号：US20230420531A1

公开(公告)日：2023-12-28

申请号：US17850769

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  YenTing CHIU ,  Orb ACTON ,  David J. TOWNER ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/0673

Abstract: Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric including a first N-type dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric including the first N-type dipole material layer and a second N-type dipole material layer.

公开(公告)号：US20230317807A1

公开(公告)日：2023-10-05

申请号：US17693150

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  YenTing CHIU ,  David J. TOWNER ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having additive gate structures in a tub architecture are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric including a first dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric including a second dipole material layer. A dielectric wall is between and in contact with the P-type gate stack and the N-type gate stack.

公开(公告)号：US20240113116A1

公开(公告)日：2024-04-04

申请号：US17958293

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  YenTing CHIU ,  Tahir GHANI ,  Leonard P. GULER ,  Mohammad HASAN ,  Aryan NAVABI-SHIRAZI ,  Anand S. MURTHY ,  Wonil CHUNG ,  Allen B. GARDINER

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/775

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrated circuit structures that include self-aligned metal gates, self-aligned epitaxial structure, self-aligned terminal contacts over the epitaxial structure, and removal of poly material around a gate during integrated circuit structure manufacture, using a tub gate architecture. Other embodiments may be described and/or claimed.

公开(公告)号：US20230290851A1

公开(公告)日：2023-09-14

申请号：US17693156

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  YenTing CHIU ,  Tahir GHANI

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having additive gate structures are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric, and an intervening conductive seed layer between the P-type conductive layer and the first gate dielectric. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric, and the intervening conductive seed layer between the N-type conductive layer and the second gate dielectric. The P-type gate stack is in contact with the N-type gate stack.

公开(公告)号：US20230290778A1

公开(公告)日：2023-09-14

申请号：US17694266

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  YenTing CHIU ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/775 ,  H01L29/78391 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6684 ,  H01L29/66742

Abstract: Gate-all-around integrated circuit structures having dual metal gates and gate dielectrics with a single polarity dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric including a high-k dielectric layer and a dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having a mid-gap conductive layer over a second gate dielectric including the high-k dielectric layer and the dipole material layer.

公开(公告)号：US20220416039A1

公开(公告)日：2022-12-29

申请号：US17357711

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  David J. TOWNER ,  Orb ACTON ,  Jitendra Kumar JHA ,  YenTing CHIU ,  Mohit K. HARAN ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L29/49

Abstract: An integrated circuit structure comprises a first and second vertical arrangement of horizontal nanowires in a PMOS region and in an NMOS region. A first gate stack having a P-type conductive layer surrounds the first vertical arrangement of horizontal nanowires. A second gate stack surrounds the second vertical arrangement of horizontal nanowires. In one embodiment, the second gate stack has an N-type conductive layer, the P-type conductive layer is over the second gate stack, and an N-type conductive fill is between N-type conductive layer and the P-type conductive layer to provide same polarity metal filled gates. In another embodiment, the second gate stack has an N-type conductive layer comprising Titanium (Ti) and “Nitrogen (N) having a low saturation thickness of 3-3.5 nm surrounding the nanowires, and the N-type conductive layer is covered by the P-type conductive layer.