公开(公告)号：US20190043874A1

公开(公告)日：2019-02-07

申请号：US15828039

申请日：2017-11-30

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Owen W. Jungroth ,  David S. Meyaard ,  Khaled Hasnat

IPC: H01L27/11531 ,  G11C16/04 ,  H01L27/11551 ,  H01L27/11578 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11573

Abstract: The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.

公开(公告)号：US10593624B2

公开(公告)日：2020-03-17

申请号：US16045369

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Aaron Yip ,  Mark Helm ,  Yongna Li

IPC: H01L21/768 ,  H01L23/528 ,  H01L49/02 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11578

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.

公开(公告)号：US10043751B2

公开(公告)日：2018-08-07

申请号：US15085151

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Aaron Yip ,  Mark Helm ,  Yongna Li

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11578

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.