公开(公告)号：US11632092B2

公开(公告)日：2023-04-18

申请号：US17315931

申请日：2021-05-10

Applicant: Intel Corporation

Inventor： Kaushik Dasgupta ,  Chuanzhao Yu ,  Chintan Thakkar ,  Saeid Daneshgar ,  Hyun Yoon ,  Xi Li ,  Anandaroop Chakrabarti ,  Stefan Shopov

IPC: H01F27/29 ,  H03F3/60 ,  H01F17/00 ,  H03F3/45 ,  H03H7/42 ,  H03F1/32

Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.

公开(公告)号：US11031918B2

公开(公告)日：2021-06-08

申请号：US16177790

申请日：2018-11-01

Applicant: Intel Corporation

Inventor： Kaushik Dasgupta ,  Chuanzhao Yu ,  Chintan Thakkar ,  Saeid Daneshgar ,  Hyun Yoon ,  Xi Li ,  Anandaroop Chakrabarti ,  Stefan Shopov

IPC: H01F27/29 ,  H03F3/60 ,  H01F17/00 ,  H03F3/45 ,  H03H7/42

Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.