公开(公告)号：US20190391940A1

公开(公告)日：2019-12-26

申请号：US16457110

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Sridhar Samudrala ,  Parthasarathy Sarangam ,  Kiran Patil

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/4401 ,  G06F3/06

Abstract: Technologies for interrupt disassociated queuing for multi-queue input/output devices includes determining whether a network packet has arrived in an interrupt-disassociated queue and delivering the network packet to an application managed by the compute node. The application is associated with an application thread and the interrupt-disassociated queue may be in a polling mode. Subsequently, in response to a transition event, the interrupt-disassociated queue may be transitioned to an interrupt mode.

公开(公告)号：US10353631B2

公开(公告)日：2019-07-16

申请号：US13948715

申请日：2013-07-23

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Dave B. Minturn ,  Kiran Patil

IPC: G06F15/167 ,  G06F3/06

Abstract: Examples are disclosed for moving data between a network input/output (I/O) device and a storage subsystem and/or storage device. In some examples, a network I/O device coupled to a host device may receive a data frame including a request to access a storage subsystem or storage device. The storage subsystem and/or storage device may be located with the network I/O device or separately coupled to the host device through a storage controller. One or more buffers maintained in a cache for processor circuitry may be used to exchange control information or stage data associated with the data frame to avoid or eliminate use of system memory to move data to or from the storage subsystem and/or storage device. Other examples are described and claimed.