Efficient receive interrupt signaling

    公开(公告)号:US11797333B2

    公开(公告)日:2023-10-24

    申请号:US16710556

    申请日:2019-12-11

    申请人: Intel Corporation

    IPC分类号: G06F9/46 G06F9/48 G06F9/50

    摘要: Methods for performing efficient receive interrupt signaling and associated apparatus, computing platform, software, and firmware. Receive (RX) queues in which descriptors associated with packets are enqueued are implemented in host memory and logically partitioned into pools, with each RX queue pool associated with a respective interrupt vector. Receive event queues (REQs) associated with respective RX queue pools and interrupt vectors are also implemented in host memory. Event generation is selectively enabled for some RX queues, while event generation is masked for others. In response to event causes for RX queues that are event generation-enabled, associated events are generated and enqueued in the REQs and interrupts on associated interrupt vectors are asserted. The events are serviced by accessing the events in the REQs, which identify the RX queue for the event and a next activity location at which a next descriptor to be processed is located. After asserting an interrupt, an RX queue may be auto-masked to prevent generation of additional events when new descriptors are enqueued in the RX queue.

    Techniques for Moving Data between a Network Input/Output Device and a Storage Device

    公开(公告)号:US20190272124A1

    公开(公告)日:2019-09-05

    申请号:US16418405

    申请日:2019-05-21

    申请人: INTEL CORPORATION

    IPC分类号: G06F3/06

    摘要: Examples are disclosed for moving data between a network input/output (I/O) device and a storage subsystem and/or storage device. In some examples, a network I/O device coupled to a host device may receive a data frame including a request to access a storage subsystem or storage device. The storage subsystem and/or storage device may be located with the network I/O device or separately coupled to the host device through a storage controller. One or more buffers maintained in a cache for processor circuitry may be used to exchange control information or stage data associated with the data frame to avoid or eliminate use of system memory to move data to or from the storage subsystem and/or storage device. Other examples are described and claimed.

    Techniques for moving data between a network input/output device and a storage device

    公开(公告)号:US10353631B2

    公开(公告)日:2019-07-16

    申请号:US13948715

    申请日:2013-07-23

    申请人: Intel Corporation

    IPC分类号: G06F15/167 G06F3/06

    摘要: Examples are disclosed for moving data between a network input/output (I/O) device and a storage subsystem and/or storage device. In some examples, a network I/O device coupled to a host device may receive a data frame including a request to access a storage subsystem or storage device. The storage subsystem and/or storage device may be located with the network I/O device or separately coupled to the host device through a storage controller. One or more buffers maintained in a cache for processor circuitry may be used to exchange control information or stage data associated with the data frame to avoid or eliminate use of system memory to move data to or from the storage subsystem and/or storage device. Other examples are described and claimed.