公开(公告)号：US20200176372A1

公开(公告)日：2020-06-04

申请号：US16481421

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Dinesh SOMASEKHAR ,  Dheeraj SUBBAREDDY

IPC: H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L23/00

Abstract: Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.

公开(公告)号：US20190230795A1

公开(公告)日：2019-07-25

申请号：US16372268

申请日：2019-04-01

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Scott A. GILBERT

IPC: H05K3/34 ,  H01L21/48 ,  H05K1/11 ,  B23K31/02 ,  H01L23/498

Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.