公开(公告)号：US12032972B2

公开(公告)日：2024-07-09

申请号：US17829315

申请日：2022-05-31

Applicant: Intel Corporation

Inventor： Anatoly Litvinov ,  Ilya Sister ,  Andrey Semenjatshenco ,  Nir Gerber

IPC: G06F1/24 ,  G06F1/3296 ,  G06F9/00 ,  G06F9/445 ,  G06F11/34 ,  G06V10/62 ,  G06V10/74 ,  G06V10/75

CPC classification number: G06F9/44505 ,  G06F1/3296 ,  G06F11/3409 ,  G06V10/62 ,  G06V10/761 ,  G06V10/758

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve performance of a compute device by detecting a scene change. An example apparatus includes scene change detection circuitry and interrupt circuitry. The example scene change detection circuitry is to determine a first score value for a first metric of similarity between a first image of a field of view (FOV) of an image sensor and a second image of the FOV, determine a second score value for a second metric of similarity between the first image and the second image, and compute a composite score value based on the first score value and the second score value. The example interrupt circuitry is to generate an interrupt to processor circuitry of the compute device to cause the processor circuitry to adjust a computation condition of the compute device based on the composite score.

公开(公告)号：US20210326191A1

公开(公告)日：2021-10-21

申请号：US17359308

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Charu Srivastava ,  Changliang Wang ,  Srikanth Potluri ,  Nir Gerber ,  Qixiong Bian ,  Stanley Baran

IPC: G06F9/54 ,  G06F13/40

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to align processing events. An example apparatus includes a comparator to compare a value of a counter to a threshold value, the threshold value associated with an amount of time to defer provision of a first or second input signal to a corresponding first or second IP device, respectively, signal deferring circuitry to defer provision of the first or second input signals to a corresponding one of the first or second IP devices based on an output of the comparator, deferral of the first or second input signals to cause alignment of first and second processing events performed by the first and second IP devices, respectively, and power controlling circuitry to cause the first and second IP devices to power down based on completion of the first and second processing events.