公开(公告)号：US11683251B2

公开(公告)日：2023-06-20

申请号：US17699963

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Eugene Yasman ,  Nir Gerber ,  Sumit Mohan ,  Jean-Pierre Giacalone

IPC: H04L43/087 ,  H04L49/9005 ,  H04L49/90 ,  H04L49/9047 ,  H04L43/16 ,  H04L12/70

CPC classification number: H04L43/087 ,  H04L43/16 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9052 ,  H04L49/9078 ,  H04L2012/5681

Abstract: Technologies for low-latency data streaming include a computing device having a processor that includes a producer and a consumer. The producer generates a data item, and in a local buffer producer mode adds the data item to a local buffer, and in a remote buffer producer mode adds the data item to a remote buffer. When the local buffer is full, the producer switches to the remote buffer producer mode, and when the remote buffer is below a predetermined low threshold, the producer switches to the local buffer producer mode. The consumer reads the data item from the local buffer while operating in a local buffer consumer mode and reads the data item from the remote buffer while operating in a remote buffer consumer mode. When the local buffer is above a predetermined high threshold, the consumer may switch to a catch-up operating mode. Other embodiments are described and claimed.

公开(公告)号：US20220291930A1

公开(公告)日：2022-09-15

申请号：US17829315

申请日：2022-05-31

Applicant: Intel Corporation

Inventor： Anatoly Litvinov ,  Ilya Sister ,  Andrey Semenjatshenco ,  Nir Gerber

IPC: G06F9/445 ,  G06V10/74 ,  G06V10/62 ,  G06F11/34 ,  G06F1/3296

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve performance of a compute device by detecting a scene change. An example apparatus includes scene change detection circuitry and interrupt circuitry. The example scene change detection circuitry is to determine a first score value for a first metric of similarity between a first image of a field of view (FOV) of an image sensor and a second image of the FOV, determine a second score value for a second metric of similarity between the first image and the second image, and compute a composite score value based on the first score value and the second score value. The example interrupt circuitry is to generate an interrupt to processor circuitry of the compute device to cause the processor circuitry to adjust a computation condition of the compute device based on the composite score.

公开(公告)号：US11283700B2

公开(公告)日：2022-03-22

申请号：US16682291

申请日：2019-11-13

Applicant: Intel Corporation

Inventor： Eugene Yasman ,  Nir Gerber ,  Sumit Mohan ,  Jean-Pierre Giacalone

IPC: H04L12/26 ,  H04L12/861 ,  H04L12/883 ,  H04L12/70 ,  H04L43/087 ,  H04L49/9005 ,  H04L49/90 ,  H04L49/9047 ,  H04L43/16

Abstract: Technologies for low-latency data streaming include a computing device having a processor that includes a producer and a consumer. The producer generates a data item, and in a local buffer producer mode adds the data item to a local buffer, and in a remote buffer producer mode adds the data item to a remote buffer. When the local buffer is full, the producer switches to the remote buffer producer mode, and when the remote buffer is below a predetermined low threshold, the producer switches to the local buffer producer mode. The consumer reads the data item from the local buffer while operating in a local buffer consumer mode and reads the data item from the remote buffer while operating in a remote buffer consumer mode. When the local buffer is above a predetermined high threshold, the consumer may switch to a catch-up operating mode. Other embodiments are described and claimed.

公开(公告)号：US20200092185A1

公开(公告)日：2020-03-19

申请号：US16682291

申请日：2019-11-13

Applicant: Intel Corporation

Inventor： Eugene Yasman ,  Nir Gerber ,  Sumit Mohan ,  Jean-Pierre Giacalone

IPC: H04L12/26 ,  H04L12/861 ,  H04L12/883

Abstract: Technologies for low-latency data streaming include a computing device having a processor that includes a producer and a consumer. The producer generates a data item, and in a local buffer producer mode adds the data item to a local buffer, and in a remote buffer producer mode adds the data item to a remote buffer. When the local buffer is full, the producer switches to the remote buffer producer mode, and when the remote buffer is below a predetermined low threshold, the producer switches to the local buffer producer mode. The consumer reads the data item from the local buffer while operating in a local buffer consumer mode and reads the data item from the remote buffer while operating in a remote buffer consumer mode. When the local buffer is above a predetermined high threshold, the consumer may switch to a catch-up operating mode. Other embodiments are described and claimed.

公开(公告)号：US20230314508A1

公开(公告)日：2023-10-05

申请号：US17712100

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： Elik Haran ,  Nir Gerber ,  Tal Davidson ,  Wei Hu ,  Nadav Levison

IPC: G01R31/3183 ,  G01R31/3187 ,  G01R31/3185

CPC classification number: G01R31/318307 ,  G01R31/318597 ,  G01R31/3187

Abstract: Embodiments of apparatuses and methods for in-field testing of an integrated circuit (IC) are disclosed. In an embodiment, an apparatus includes an IC having circuitry to operate in a structural test mode, the structural test mode including a memory built-in self-test (MBIST) mechanism and an automatic test pattern generation (ATPG) mechanism; a microcontroller to enable and control the structural test mode during in-field operation of the IC; and a programmable logic device to support the ATPG mechanism.

公开(公告)号：US20220210037A1

公开(公告)日：2022-06-30

申请号：US17699963

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Eugene Yasman ,  Nir Gerber ,  Sumit Mohan ,  Jean-Pierre Giacalone

IPC: H04L43/087 ,  H04L49/9005 ,  H04L49/90 ,  H04L49/9047 ,  H04L43/16

Abstract: Technologies for low-latency data streaming include a computing device having a processor that includes a producer and a consumer. The producer generates a data item, and in a local buffer producer mode adds the data item to a local buffer, and in a remote buffer producer mode adds the data item to a remote buffer. When the local buffer is full, the producer switches to the remote buffer producer mode, and when the remote buffer is below a predetermined low threshold, the producer switches to the local buffer producer mode. The consumer reads the data item from the local buffer while operating in a local buffer consumer mode and reads the data item from the remote buffer while operating in a remote buffer consumer mode. When the local buffer is above a predetermined high threshold, the consumer may switch to a catch-up operating mode. Other embodiments are described and claimed.

公开(公告)号：US10511509B2

公开(公告)日：2019-12-17

申请号：US15481708

申请日：2017-04-07

Applicant: INTEL CORPORATION

Inventor： Eugene Yasman ,  Nir Gerber ,  Sumit Mohan ,  Jean-Pierre Giacalone

IPC: H04L12/26 ,  H04L12/861 ,  H04L12/883 ,  H04L12/70

Abstract: Technologies for low-latency data streaming include a computing device having a processor that includes a producer and a consumer. The producer generates a data item, and in a local buffer producer mode adds the data item to a local buffer, and in a remote buffer producer mode adds the data item to a remote buffer. When the local buffer is full, the producer switches to the remote buffer producer mode, and when the remote buffer is below a predetermined low threshold, the producer switches to the local buffer producer mode. The consumer reads the data item from the local buffer while operating in a local buffer consumer mode and reads the data item from the remote buffer while operating in a remote buffer consumer mode. When the local buffer is above a predetermined high threshold, the consumer may switch to a catch-up operating mode. Other embodiments are described and claimed.

公开(公告)号：US10915258B2

公开(公告)日：2021-02-09

申请号：US15857158

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Eugene Yasman ,  Liron Ain-Kedem ,  Nir Gerber

IPC: G06F3/06 ,  H04L12/70

Abstract: Systems and techniques for bi-directional negotiation for dynamic data chunking are described herein. A set of available features for a memory subsystem. The set of available features including latency of buffer locations of the memory subsystem. An indication of a first latency requirement of a first data consumer and a second latency requirement of a second data consumer may be obtained. A first buffer location of the memory subsystem for a data stream based on the first latency requirement may be negotiated with the first data consumer. A second buffer location of the memory subsystem for the data stream based on the second latency requirement may be negotiated with the second data consumer. An indication of the first buffer location may be provided to the first data consumer and an indication of the second buffer location may be provided to the second data consumer.

公开(公告)号：US20190042123A1

公开(公告)日：2019-02-07

申请号：US15857158

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Eugene Yasman ,  Liron Ain-Kedem ,  Nir Gerber

IPC: G06F3/06

Abstract: Systems and techniques for bi-directional negotiation for dynamic data chunking are described herein. A set of available features for a memory subsystem. The set of available features including latency of buffer locations of the memory subsystem. An indication of a first latency requirement of a first data consumer and a second latency requirement of a second data consumer may be obtained. A first buffer location of the memory subsystem for a data stream based on the first latency requirement may be negotiated with the first data consumer. A second buffer location of the memory subsystem for the data stream based on the second latency requirement may be negotiated with the second data consumer. An indication of the first buffer location may be provided to the first data consumer and an indication of the second buffer location may be provided to the second data consumer.

公开(公告)号：US20180295039A1

公开(公告)日：2018-10-11

申请号：US15481708

申请日：2017-04-07

Applicant: INTEL CORPORATION

Inventor： Eugene Yasman ,  Nir Gerber ,  Sumit Mohan ,  Jean-Pierre Giacalone

IPC: H04L12/26 ,  H04L12/861 ,  H04L12/883

CPC classification number: H04L43/087 ,  H04L43/16 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9052 ,  H04L49/9078 ,  H04L2012/5681

Abstract: Technologies for low-latency data streaming include a computing device having a processor that includes a producer and a consumer. The producer generates a data item, and in a local buffer producer mode adds the data item to a local buffer, and in a remote buffer producer mode adds the data item to a remote buffer. When the local buffer is full, the producer switches to the remote buffer producer mode, and when the remote buffer is below a predetermined low threshold, the producer switches to the local buffer producer mode. The consumer reads the data item from the local buffer while operating in a local buffer consumer mode and reads the data item from the remote buffer while operating in a remote buffer consumer mode. When the local buffer is above a predetermined high threshold, the consumer may switch to a catch-up operating mode. Other embodiments are described and claimed.