公开(公告)号：US10712804B2

公开(公告)日：2020-07-14

申请号：US15847624

申请日：2017-12-19

Applicant: Intel Corporation

Inventor： Arun Kumar Singh ,  Qixiong Bian ,  Vishwanath Somayaji

IPC: G06F1/32 ,  G01J5/02 ,  G06F1/3234 ,  G06F3/01 ,  H04N21/00 ,  H04N11/24

Abstract: An apparatus is provided which comprises: a first circuitry to provide an estimate of a distance of a user from the apparatus; and a second circuitry to select a display resolution for displaying on a display panel of the apparatus, based at least in part on the estimate of the distance of the user from the apparatus.

公开(公告)号：US20190041963A1

公开(公告)日：2019-02-07

申请号：US15847624

申请日：2017-12-19

Applicant: Intel Corporation

Inventor： Arun Kumar Singh ,  Qixiong Bian ,  Vishwanath Somayaji

IPC: G06F1/32 ,  G01J5/02

Abstract: An apparatus is provided which comprises: a first circuitry to provide an estimate of a distance of a user from the apparatus; and a second circuitry to select a display resolution for displaying on a display panel of the apparatus, based at least in part on the estimate of the distance of the user from the apparatus.

公开(公告)号：US20210326191A1

公开(公告)日：2021-10-21

申请号：US17359308

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Charu Srivastava ,  Changliang Wang ,  Srikanth Potluri ,  Nir Gerber ,  Qixiong Bian ,  Stanley Baran

IPC: G06F9/54 ,  G06F13/40

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to align processing events. An example apparatus includes a comparator to compare a value of a counter to a threshold value, the threshold value associated with an amount of time to defer provision of a first or second input signal to a corresponding first or second IP device, respectively, signal deferring circuitry to defer provision of the first or second input signals to a corresponding one of the first or second IP devices based on an output of the comparator, deferral of the first or second input signals to cause alignment of first and second processing events performed by the first and second IP devices, respectively, and power controlling circuitry to cause the first and second IP devices to power down based on completion of the first and second processing events.