公开(公告)号：US20190319804A1

公开(公告)日：2019-10-17

申请号：US16456187

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： SANU MATHEW ,  MANOJ SASTRY ,  SANTOSH GHOSH ,  VIKRAM SURESH ,  ANDREW H. REINDERS ,  RAGHAVAN KUMAR ,  RAFAEL MISOCZKI

IPC: H04L9/32 ,  G06F21/76 ,  H04L9/08

Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments, according to one embodiment. A method of embodiments, as described herein, includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.

公开(公告)号：US20190319803A1

公开(公告)日：2019-10-17

申请号：US16456064

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： RAFAEL MISOCZKI ,  VIKRAM SURESH ,  SANTOSH GHOSH ,  MANOJ SASTRY ,  SANU MATHEW ,  RAGHAVAN KUMAR

IPC: H04L9/32 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

公开(公告)号：US20180088927A1

公开(公告)日：2018-03-29

申请号：US15278658

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： LI ZHAO ,  RAFAEL MISOCZKI ,  SANTOSH GHOSH ,  MANOJ R. SASTRY

IPC: G06F9/445 ,  G06F9/44 ,  H04L9/30 ,  H04L9/32 ,  H04L9/06 ,  H04L29/06

CPC classification number: H04L9/0643 ,  G06F21/575 ,  H04L9/0836 ,  H04L9/3236 ,  H04L9/3247 ,  H04L63/123 ,  H04L2209/38

Abstract: One embodiment provides an apparatus. The apparatus includes an Internet of Things (IoT) device including a processor, a memory, a flash memory, a network interface and a boot Read Only Memory (ROM). A Root-of-Trust (RoT) application stored in the boot ROM causes the processor run the RoT after initialization of the IoT device. The RoT causes the device to determine a selected image by determining if an update mode is set. The RoT also causes the processor to load the selected image into memory and determine whether a verification of a signature of the selected image is successful. When the verification of the signature is successful then control is transferred to the selected image and when the verification is not successful then a recovery boot is performed