公开(公告)号：US20220224514A1

公开(公告)日：2022-07-14

申请号：US17707629

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： SANTOSH GHOSH ,  VIKRAM SURESH ,  SANU MATHEW ,  MANOJ SASTRY ,  ANDREW H. REINDERS ,  RAGHAVAN KUMAR ,  RAFAEL MISOCZKI

IPC: H04L9/06 ,  G06F7/503 ,  G06F9/30 ,  H04L9/32

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

公开(公告)号：US20190319804A1

公开(公告)日：2019-10-17

申请号：US16456187

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： SANU MATHEW ,  MANOJ SASTRY ,  SANTOSH GHOSH ,  VIKRAM SURESH ,  ANDREW H. REINDERS ,  RAGHAVAN KUMAR ,  RAFAEL MISOCZKI

IPC: H04L9/32 ,  G06F21/76 ,  H04L9/08

Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments, according to one embodiment. A method of embodiments, as described herein, includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.

公开(公告)号：US20190319803A1

公开(公告)日：2019-10-17

申请号：US16456064

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： RAFAEL MISOCZKI ,  VIKRAM SURESH ,  SANTOSH GHOSH ,  MANOJ SASTRY ,  SANU MATHEW ,  RAGHAVAN KUMAR

IPC: H04L9/32 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

公开(公告)号：US20220085993A1

公开(公告)日：2022-03-17

申请号：US17019864

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： RAGHAVAN KUMAR ,  SUDHIR SATPATHY ,  VIKRAM SURESH ,  SANU MATHEW

IPC: H04L9/08 ,  H04L9/32 ,  H04L9/30

Abstract: An apparatus includes a processor to generate a random exponent having a fixed bit width, divide the random exponent into a pre-exponent portion and a post-exponent portion at a random bit position in the fixed bit width, and generate a cryptographic key using the pre-exponent portion and the post exponent portion

公开(公告)号：US20180097625A1

公开(公告)日：2018-04-05

申请号：US15283323

申请日：2016-10-01

Applicant: INTEL CORPORATION

Inventor： SUDHIR K. SATPATHY ,  RAGHAVAN KUMAR ,  SANU K. MATHEW ,  VIKRAM B. SURESH

IPC: H04L9/30 ,  G09C1/00 ,  G06F7/72

CPC classification number: H04L9/302 ,  G06F7/728 ,  G09C1/00 ,  H04L2209/125

Abstract: Computing devices and techniques for performing modular exponentiation for a data encryption process are described. In one embodiment, for example, an apparatus may include at least one memory logic for an encryption unit to perform encryption according to RSA encryption using a parallel reduction multiplier (PRM) MM process, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one wireless transmitter, the logic to precompute a reduction coefficient, determine an operand product and a reduction product in parallel, the reduction product based on the reduction coefficient, and generate a MM result for the PRM MM process based on the operand product and the reduction product. Other embodiments are described and claimed.

公开(公告)号：US20230017447A1

公开(公告)日：2023-01-19

申请号：US17934682

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： SANU MATHEW ,  MANOJ SASTRY ,  SANTOSH GHOSH ,  VIKRAM SURESH ,  ANDREW H. REINDERS ,  RAGHAVAN KUMAR ,  RAFAEL MISOCZKI

IPC: H04L9/32 ,  G06F21/76 ,  H04L9/08

Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments, according to one embodiment. A method of embodiments, as described herein, includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.

公开(公告)号：US20190319797A1

公开(公告)日：2019-10-17

申请号：US16455908

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： VIKRAM SURESH ,  SANU MATHEW ,  MANOJ SASTRY ,  SANTOSH GHOSH ,  RAGHAVAN KUMAR ,  RAFAEL MISOCZKI

IPC: H04L9/32 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.

公开(公告)号：US20220337421A1

公开(公告)日：2022-10-20

申请号：US17854911

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： SANTOSH GHOSH ,  VIKRAM SURESH ,  SANU MATHEW ,  MANOJ SASTRY ,  ANDREW H. REINDERS ,  RAGHAVAN KUMAR ,  RAFAEL MISOCZKI

IPC: H04L9/32 ,  H04L9/08 ,  H04L9/06 ,  H04L9/30

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

公开(公告)号：US20220086010A1

公开(公告)日：2022-03-17

申请号：US17534158

申请日：2021-11-23

Applicant: Intel Corporation

Inventor： VIKRAM SURESH ,  SANU MATHEW ,  MANOJ SASTRY ,  SANTOSH GHOSH ,  RAGHAVAN KUMAR ,  RAFAEL MISOCZKI

IPC: H04L9/32 ,  H04L9/06 ,  G06F9/38 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

公开(公告)号：US20190007223A1

公开(公告)日：2019-01-03

申请号：US15640469

申请日：2017-07-01

Applicant: INTEL CORPORATION

Inventor： VAIBHAV VAIDYA ,  SANU K. MATHEW ,  SUDHIR K. SATPATHY ,  RAGHAVAN KUMAR

IPC: H04L9/38 ,  H04L9/06

Abstract: Various embodiments are generally directed to techniques to power encryption circuitry, such as with a power converter, for instance. Some embodiments are particularly directed to a power converter that utilizes one or more capacitors to power encryption circuitry while masking the power signature of the encryption circuitry. In one or more embodiments, for example, a power converter may charge a capacitor with a power source of a computing platform, and then power encryption circuitry with the capacitor to perform a first portion of an encryption operation. In one or more such embodiments, the power converter may recharge the capacitor with the power source after completion of the first portion of the encryption operation, and perform a second portion of the encryption operation.