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    FAST XMSS SIGNATURE VERIFICATION AND NONCE SAMPLING PROCESS WITHOUT SIGNATURE EXPANSION
    5.
    发明申请
    FAST XMSS SIGNATURE VERIFICATION AND NONCE SAMPLING PROCESS WITHOUT SIGNATURE EXPANSION 审中-公开

    公开(公告)号：US20190319800A1

    公开(公告)日：2019-10-17

    申请号：US16455967

    申请日：2019-06-28

    Applicant: Intel Corporation

    Inventor： RAFAEL MISOCZKI ,  VIKRAM SURESH ,  DAVID WHEELER ,  SANTOSH GHOSH ,  MANOJJ SASTRY

    IPC: H04L9/32 ,  H04L9/06

    Abstract: In one example an apparatus comprises accelerator logic to pre-compute at least a portion of a message representative, hash logic to generate the message representative based on an input message, and signature logic to generate a signature to be transmitted in association with the message representative, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and determine whether the message representative satisfies a target threshold allocation of computational costs between a cost to generate the signature and a cost to verify the signature. Other examples may be described.

    ODD INDEX PRECOMPUTATION FOR AUTHENTICATION PATH COMPUTATION
    9.
    发明申请
    ODD INDEX PRECOMPUTATION FOR AUTHENTICATION PATH COMPUTATION 审中-公开

    公开(公告)号：US20190319803A1

    公开(公告)日：2019-10-17

    申请号：US16456064

    申请日：2019-06-28

    Applicant: Intel Corporation

    Inventor： RAFAEL MISOCZKI ,  VIKRAM SURESH ,  SANTOSH GHOSH ,  MANOJ SASTRY ,  SANU MATHEW ,  RAGHAVAN KUMAR

    IPC: H04L9/32 ,  H04L9/08

    Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

    TECHNIQUES FOR SECURE AUTHENTICATION
    10.
    发明申请
    TECHNIQUES FOR SECURE AUTHENTICATION 审中-公开

    公开(公告)号：US20180097630A1

    公开(公告)日：2018-04-05

    申请号：US15283315

    申请日：2016-10-01

    Applicant: INTEL CORPORATION

    Inventor： VIKRAM SURESH ,  SUDHIR SATPATHY ,  SANU MATHEW

    IPC: H04L9/32 ,  H04L9/06 ,  G06F7/72 ,  G06F17/16

    CPC classification number: H04L9/3236 ,  G06F7/724 ,  G09C1/00 ,  H04L9/0643 ,  H04L2209/12 ,  H04L2209/24

    Abstract: Various embodiments are generally directed to techniques for secure message authentication and digital signatures, such as with a cipher-based hash function, for instance. Some embodiments are particularly directed to a secure authentication system that implements various aspects of the cipher-based hash function in dedicated hardware or circuitry. In various embodiments, the secure authentication system may implement one or more elements of the Whirlpool hash function in dedicated hardware. For instance, the compute-intensive substitute byte and mix rows blocks of the block cipher in the Whirlpool hash function may be implemented in dedicated hardware or circuitry using a combination of Galois Field arithmetic and fused scale/reduce circuits. In some embodiments, the microarchitecture of the secure authentication system may be implemented with delayed add key to limit the memory requirement to three sequential registers.

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