公开(公告)号：US10715144B2

公开(公告)日：2020-07-14

申请号：US16434088

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Sergey Gribok ,  Gregg Baeckler ,  Martin Langhammer

IPC: H03K19/0175 ,  H03K19/20 ,  H03K19/1778 ,  G06F7/50 ,  G06F7/53

Abstract: Integrated circuits with programmable logic regions are provided. The programmable logic regions may be organized into smaller logic units sometimes referred to as a logic cell. A logic cell may include four 4-input lookup tables (LUTs) coupled to an adder carry chain. Each of the four 4-input LUTs may include two 3-input LUTs and a selector multiplexer. The carry chain may include at three or more full adder circuits. The outputs of the 3-input LUTs may be directly connected to inputs of the full adder circuits in the carry chain. By providing at least the same or more number of full adder circuits as the total number of 4-input LUTs in the logic cell, the arithmetic density of the logic is enhanced.

公开(公告)号：US20200142671A1

公开(公告)日：2020-05-07

申请号：US16231170

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Bogdan Pasca ,  Martin Langhammer ,  Sergey Gribok ,  Gregg William Baeckler

IPC: G06F7/523 ,  H03K19/177

Abstract: Integrated circuits with digital signal processing (DSP) blocks are provided. A DSP block may include one or more large multiplier circuits. A large multiplier circuit such as an 18×18 multiplier circuit may be used to support two or more smaller multiplication operations such as two 8×8 integer multiplications or two 9×9 integer multiplications. To implement the two 8×8 or 9×9 unsigned/signed multiplications, the 18×18 multiplier may be configured to support two 8×8 multiplications with one shared operand, two 6×6 multiplications without any shared operand, or two 7×7 multiplications without any shared operand. Any potential overlap of partial product terms may be subtracted out using correction logic. The multiplication of the remaining most significant bits can be computed using associated multiplier extension logic and appended to the other least significant bits using merging logic.

公开(公告)号：US20200106442A1

公开(公告)日：2020-04-02

申请号：US16144558

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Sergey Gribok ,  Gregg William Baeckler

IPC: H03K19/177 ,  H03K19/173 ,  G06F7/501 ,  G06F7/523

Abstract: Integrated circuits with programmable logic regions are provided. The programmable logic regions may be organized into smaller logic units sometimes referred to as a logic element. A logic element may include four lookup tables coupled to an adder carry chain. At least some of the lookup tables are configured to output combinatorial outputs, whereas the adder carry chain are used to output sum outputs. Both the combinatorial outputs and the sum outputs may be used simultaneously to support a multiplication operation, three or more logic operations, or arithmetic and combinatorial operations in parallel.

公开(公告)号：US20200026494A1

公开(公告)日：2020-01-23

申请号：US16585857

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Bogdan Pasca ,  Sergey Gribok ,  Gregg William Baeckler ,  Andrei Hagiescu

IPC: G06F7/487 ,  G06F7/501 ,  G06F17/16 ,  G06F9/30 ,  H03M7/24

Abstract: A programmable device may be configured to support machine learning training operations using matrix multiplication circuitry implemented on a systolic array. The systolic array includes an array of processing elements, each of which includes hybrid floating-point dot-product circuitry. The hybrid dot-product circuitry has a hard data path that uses digital signal processing (DSP) blocks operating in floating-point mode and a hard/soft data path that uses DSP blocks operating in fixed-point mode operated in conjunction with general purpose soft logic. The hard/soft data path includes 2-element dot-product circuits that feed an adder tree. Results from the hard data path are combined with the adder tree using format conversion and normalization circuitry. Inputs to the hybrid dot-product circuitry may be in the BFLOAT16 format. The hard data path may be in the single precision format. The hard/soft data path uses a custom format that is similar to but different than BFLOAT16.