公开(公告)号：US20230222275A1

公开(公告)日：2023-07-13

申请号：US18122612

申请日：2023-03-16

Applicant: Intel Corporation

Inventor： Gregg Baeckler ,  Mahesh A. Iyer ,  Martin Langhammer

IPC: G06F30/327

CPC classification number: G06F30/327 ,  G06F2111/04

Abstract: A method is provided for processing code for a circuit design for an integrated circuit using a computer system. The method includes receiving at least a portion of the code for the circuit design for the integrated circuit, wherein the portion of the code comprises an error or has incomplete constraints, making an assumption about the error and the missing constraints using a computer aid design tool, and generating a revised circuit design for the integrated circuit with the error corrected and any missing constraints added based on the assumption and based on the code using the computer aided design tool and a library of components for circuit designs.

公开(公告)号：US20230116554A1

公开(公告)日：2023-04-13

申请号：US18077170

申请日：2022-12-07

Applicant: Intel Corporation

Inventor： Gregg Baeckler ,  Martin Langhammer

IPC: G06F8/41

Abstract: A processor circuit includes a compiler configured to receive a software program that comprises software code coded in an assembly language and inline software code coded in a high-level programming language, compile the inline software code coded in the high-level programming language within the software program into assembly code in the assembly language, and compile the assembly code and the software code coded in the assembly language into machine code for the processor circuit. A method includes determining if first and second instructions in a software program are combinable into one instruction word, combining the first and the second instructions in the software program into one instruction word if the first and the second instructions are combinable, and fetching the instruction word into a single register by storing the instruction word in the single register.

公开(公告)号：US20190288688A1

公开(公告)日：2019-09-19

申请号：US16434088

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Sergey Gribok ,  Gregg Baeckler ,  Martin Langhammer

IPC: H03K19/0175 ,  H03K19/177 ,  G06F7/50 ,  H03K19/20

Abstract: Integrated circuits with programmable logic regions are provided. The programmable logic regions may be organized into smaller logic units sometimes referred to as a logic cell. A logic cell may include four 4-input lookup tables (LUTs) coupled to an adder carry chain. Each of the four 4-input LUTs may include two 3-input LUTs and a selector multiplexer. The carry chain may include at three or more full adder circuits. The outputs of the 3-input LUTs may be directly connected to inputs of the full adder circuits in the carry chain. By providing at least the same or more number of full adder circuits as the total number of 4-input LUTs in the logic cell, the arithmetic density of the logic is enhanced.

公开(公告)号：US10715144B2

公开(公告)日：2020-07-14

申请号：US16434088

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Sergey Gribok ,  Gregg Baeckler ,  Martin Langhammer

IPC: H03K19/0175 ,  H03K19/20 ,  H03K19/1778 ,  G06F7/50 ,  G06F7/53

Abstract: Integrated circuits with programmable logic regions are provided. The programmable logic regions may be organized into smaller logic units sometimes referred to as a logic cell. A logic cell may include four 4-input lookup tables (LUTs) coupled to an adder carry chain. Each of the four 4-input LUTs may include two 3-input LUTs and a selector multiplexer. The carry chain may include at three or more full adder circuits. The outputs of the 3-input LUTs may be directly connected to inputs of the full adder circuits in the carry chain. By providing at least the same or more number of full adder circuits as the total number of 4-input LUTs in the logic cell, the arithmetic density of the logic is enhanced.

公开(公告)号：US20180364981A1

公开(公告)日：2018-12-20

申请号：US15718978

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Gregg Baeckler

IPC: G06F7/523 ,  G06F7/48

Abstract: Systems, methods, and devices for enhancing performance/efficiency of soft multiplier implementations are provided. More specifically, a method to implement soft multipliers with a high radix subset code architecture is provided. The techniques provided herein result in smaller multipliers that consume less area, improve packing, consume less power, and improve routing options on an integrated circuit.

公开(公告)号：US11010134B2

公开(公告)日：2021-05-18

申请号：US15718978

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Gregg Baeckler

IPC: G06F7/533 ,  G06F7/523 ,  G06F7/48

Abstract: Systems, methods, and devices for enhancing performance/efficiency of soft multiplier implementations are provided. More specifically, a method to implement soft multipliers with a high radix subset code architecture is provided. The techniques provided herein result in smaller multipliers that consume less area, improve packing, consume less power, and improve routing options on an integrated circuit.