公开(公告)号：US11688634B2

公开(公告)日：2023-06-27

申请号：US16526012

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Vipul Mehta ,  Yiqun Bai ,  Ziyin Lin ,  John Decker ,  Yan Li

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/768 ,  H01L23/373 ,  H01L23/367

CPC classification number: H01L21/76877 ,  H01L21/565 ,  H01L21/76804 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/373

Abstract: Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench.

公开(公告)号：US20220309124A1

公开(公告)日：2022-09-29

申请号：US17211627

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Chunhui Mei ,  Hong Jiang ,  Jiasheng Chen ,  Yongsheng Liu ,  Yan Li

IPC: G06F17/16 ,  G06F17/11 ,  G06F15/80 ,  G06F7/544 ,  G06F9/30

Abstract: Matrix multiply units can take advantage of input sparsity by zero gating ALUs, which saves power consumption, but compute throughput does not increase. To improve compute throughput from sparsity, processing resources in a matrix accelerator can skip computation with zero involved in input or output. If zeros in input can be skipped, the processing units can focus calculations on generating meaningful non-zero output.