公开(公告)号：US12132009B2

公开(公告)日：2024-10-29

申请号：US18143932

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Chang Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/29

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/18 ,  H01L23/295 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the semiconductor chip and the dummy chip in the direction perpendicular to the first surface of the substrate, an upper end of the extension portion being disposed to be lower than the upper surface of the semiconductor chip; and a sealing material disposed on the first surface of the substrate, and sealing the semiconductor chip and the dummy chip.

公开(公告)号：US20240347409A1

公开(公告)日：2024-10-17

申请号：US18747798

申请日：2024-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingu Kim ,  Sangkyu Lee ,  Yongkoon Lee ,  Seokkyu Choi

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor package includes a connection layer, a semiconductor chip disposed at a center portion of the connection layer, an adhesive layer disposed on the semiconductor chip, a heat spreader layer disposed on the adhesive layer, and a lower redistribution layer disposed on the connection layer and a bottom surface of the semiconductor chip. A width of the adhesive layer is the same as a width of the semiconductor chip, and a width of the heat spreader layer is less than the width of the adhesive layer.

公开(公告)号：US20240332128A1

公开(公告)日：2024-10-03

申请号：US18129567

申请日：2023-03-31

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Cyprian Emeka Uzoh ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/46 ,  H01L23/367 ,  H01L23/433

CPC classification number: H01L23/46 ,  H01L23/367 ,  H01L23/433

Abstract: Embodiments herein provide for device packages comprising an integrated cooling assembly and methods of cooling packaged devices. The integrated cooling assembly comprising a semiconductor device, a manifold attached to the semiconductor device, and a sonic transducer attached to the manifold. The manifold comprises a top portion and a waveguide extending downwardly from the top portion. The sonic transducer is attached to the top portion. The top portion, the waveguide, and a backside of the semiconductor device collectively define a coolant chamber volume therebetween.

公开(公告)号：US20240332113A1

公开(公告)日：2024-10-03

申请号：US18193932

申请日：2023-03-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Hsieh ,  Li-Hui Cheng ,  Pu Wang ,  Ying-Ching Shih

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L23/367 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/5383 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H10B80/00 ,  H01L2224/26175 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455

Abstract: An integrated circuit (IC) device includes a substrate, such as a printed circuit board (PCB) substrate. A chip assembly is disposed over the substrate. The chip assembly includes an IC, a plurality of electronic memory devices coupled to the IC, and a molding compound material that circumferentially surrounds the IC and the electronic memory devices collectively in a top view. A thermal interface material (TIM) is disposed over the chip assembly. The TIM includes an indium alloy, a gallium alloy, or an alloy that contains bismuth, indium, and tin. An adhesive dam is disposed over the substrate. The adhesive dam surrounds the chip assembly and the TIM laterally. A lid structure is disposed over the substrate and encapsulates the chip assembly therein. The lid structure includes one or more openings that expose portions of the TIM. The one or more openings accommodate an expansion of the TIM.

公开(公告)号：US12107028B2

公开(公告)日：2024-10-01

申请号：US18305913

申请日：2023-04-24

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： KyungOe Kim ,  Wagno Alves Braganca, Jr. ,  DongSam Park

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/367 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/565 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.

公开(公告)号：US20240321678A1

公开(公告)日：2024-09-26

申请号：US18606991

申请日：2024-03-15

Applicant: Smarter Silicon (Shanghai) Technologies Co., Ltd.

Inventor： SHIH-YUEH HUANG ,  Kaiyou QIAN

IPC: H01L23/42 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/42 ,  H01L23/367 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29076 ,  H01L2224/32245 ,  H01L2224/83201

Abstract: A chip packaging structure includes a chip, a heat sink, and a thermal conductive layer. The heat sink and the chip are fixed by thermal contact through the thermal conductive layer. The thermal conductive layer includes a stress buffer layer and a plurality of thermal conductive protrusions located in the stress buffer layer. Bottoms of the plurality of thermal conductive protrusions are located on a surface of the chip or a surface of the heat sink.

公开(公告)号：US20240321669A1

公开(公告)日：2024-09-26

申请号：US18380854

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggu Kang ,  JAE CHOON KIM ,  SUNG-HO MUN ,  Hwanjoo Park

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/105 ,  H10B80/00 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32245

Abstract: A semiconductor package includes a substrate, a semiconductor die on the substrate, a heat spreader covering the semiconductor die. The heat spreader includes an upper plate portion, a base portion, and a sidewall portion connecting the upper plate portion to the base portion. The upper plate portion and the sidewall portion define an underlying cavity. The base portion is disposed on the substrate, extends from an exterior side of the sidewall portion in a horizontal direction, includes a plurality of first through holes, has a bottom surface at the same level as a bottom surface of the sidewall portion, and has a height in a vertical direction from a lowermost portion to an uppermost portion thereof less than or equal to that of the sidewall portion.

公开(公告)号：US20240304512A1

公开(公告)日：2024-09-12

申请号：US18182072

申请日：2023-03-10

Applicant: Cisco Technology, Inc.

Inventor： Norbert SCHLEPPLE ,  Vipulkumar K. PATEL ,  Aparna R. PRASAD ,  Paul TON

IPC: H01L23/367 ,  G02B6/38 ,  H01L23/50

CPC classification number: H01L23/367 ,  G02B6/3897 ,  H01L23/50

Abstract: An apparatus includes a substrate, an integrated circuit positioned on the substrate, and a load plate positioned on the integrated circuit such that the load plate is arranged to absorb heat from the integrated circuit. The load plate includes a body and an extender. The body includes an upper surface and a bottom surface. The bottom surface contacts the integrated circuit such that the bottom surface is between the integrated circuit and the upper surface. A portion of the body extends beyond the integrated circuit. The extender is coupled to the portion of the body such that the extender extends from the bottom surface to define a cavity between the extender and the integrated circuit. The extender defines an aperture aligned with the integrated circuit.

公开(公告)号：US20240304464A1

公开(公告)日：2024-09-12

申请号：US18297361

申请日：2023-04-07

Applicant: OIP Technology Pte Ltd.

Inventor： Yonggang JIN

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L23/49 ,  H01L23/492 ,  H01L25/065

CPC classification number: H01L21/4882 ,  H01L21/4875 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3736 ,  H01L23/49 ,  H01L23/492 ,  H01L25/0655

Abstract: A semiconductor package and a method of fabricating the same are disclosed. The method includes: forming a heat sink on back side of at least one die and a vertical access wiring structure adjacently around and spaced apart from the die by printing process; and forming first conductive structure on front side of the plastic encapsulation layer and second conductive structure on back side of the plastic encapsulation layer. The first conductive structure is electrically connected to the die, and the second conductive structure is connected to the heat sink from back side. The first conductive structure is electrically connected to the second conductive structure by the vertical access wiring structure. The vertical access wiring structure is a solid structure, which can overcome problems that may arise from the use of conventional in-hole hollow metal shells that could not withstand large instantaneous currents possibly present in high-power multi-die integration applications.

公开(公告)号：US12087662B1

公开(公告)日：2024-09-10

申请号：US18333130

申请日：2023-06-12

Applicant: Chun-Ming Lin

Inventor： Chun-Ming Lin

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L25/065

CPC classification number: H01L23/3736 ,  H01L23/3107 ,  H01L23/367 ,  H01L24/05 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32245

Abstract: The present disclosure provides a package structure and a method for forming a package structure. The package structure includes a first die having a front surface and a back surface opposite to the front surface; and a thermal management structure over the back surface. The thermal management structure includes a first copper-phosphorous alloy layer thermally coupled to the back surface of the first die.