公开(公告)号：US09768788B2

公开(公告)日：2017-09-19

申请号：US15194533

申请日：2016-06-27

Applicant: INTEL CORPORATION

Inventor： Gennady Goltman ,  Yongping Fan ,  Kuan-Yueh Shen

IPC: H03L7/06 ,  H03L7/08 ,  H03L7/085 ,  H03L7/089 ,  H03L7/093

CPC classification number: H03L7/0802 ,  H03L7/085 ,  H03L7/089 ,  H03L7/0895 ,  H03L7/093

Abstract: Described is a phase-locked loop with lower power charge pump. The phase-locked loop comprises: a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse based on the comparison, a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and a voltage-controlled oscillator (VCO), wherein the oscillating frequency of the VCO is controlled by the control signal.

公开(公告)号：US20150194970A1

公开(公告)日：2015-07-09

申请号：US14129505

申请日：2013-11-08

Applicant: INTEL CORPORATION

Inventor： Gennady Goltman ,  Yongping Fan ,  Kuan-Yueh Shen

IPC: H03L7/08 ,  H03L7/085

CPC classification number: H03L7/0802 ,  H03L7/085 ,  H03L7/089 ,  H03L7/0895 ,  H03L7/093

Abstract: Described is an apparatus to lower power of a charge pump. The apparatus comprises: a first delay unit to receive a reference clock, the first delay unit to provide a delayed reference clock to a first sequential unit; a second delay unit to receive a feedback clock, the second delay unit to provide a delayed feedback clock to a second sequential unit; a first logic unit to receive the reference and feedback clocks, the logic unit to perform a logical OR operation on the received reference and feedback clocks, and to generate a trigger signal for a third sequential unit; and a second logic unit to receive outputs of first and second sequential units, and to generate an output coupled to the third sequential unit.

Abstract translation: 描述了一种降低电荷泵功率的装置。 所述装置包括：第一延迟单元，用于接收参考时钟，所述第一延迟单元向第一顺序单元提供延迟的参考时钟; 第二延迟单元，用于接收反馈时钟，所述第二延迟单元向第二顺序单元提供延迟的反馈时钟; 用于接收参考和反馈时钟的第一逻辑单元，所述逻辑单元对所接收的参考和反馈时钟执行逻辑或运算，并且产生用于第三顺序单元的触发信号; 以及第二逻辑单元，用于接收第一和第二顺序单元的输出，并且产生耦合到第三顺序单元的输出。