公开(公告)号：US20210366415A1

公开(公告)日：2021-11-25

申请号：US17394550

申请日：2021-08-05

Applicant: Japan Display Inc.

Inventor： Hirotaka HAYASHI

IPC: G09G3/34 ,  G09G3/36

Abstract: According to one embodiment, a display device includes a controller. The controller is configured to control voltages between the common electrode and pixel electrodes in first periods included in one frame period and control an operation of a light source in second periods included in the one frame period. The controller controls, in a first first period of the first periods included in the one frame period, the voltages between the common electrode and the pixel electrodes to write, following an immediately preceding one frame period, a video component of a same color as a color of a video component written by applying voltages between the common electrode and the pixel electrodes in a last first period of the first periods included in the immediately preceding one frame period.

公开(公告)号：US20210273108A1

公开(公告)日：2021-09-02

申请号：US17184708

申请日：2021-02-25

Applicant: Japan Display Inc.

Inventor： Hirotaka HAYASHI ,  Masataka IKEDA

IPC: H01L29/786 ,  G02F1/167

Abstract: According to one embodiment, a semiconductor layer includes a base, a scanning line disposed over the base, a signal line disposed over the base, a transistor overlapping the scanning line and the signal line and including a first oxide semiconductor layer connected to the signal line, and second oxide semiconductor layers disposed in a same layer as the first oxide semiconductor layer. The second oxide semiconductor layers are disposed around the transistor, and the second oxide semiconductor layers are floating.

公开(公告)号：US20210142754A1

公开(公告)日：2021-05-13

申请号：US17155316

申请日：2021-01-22

Applicant: Japan Display Inc.

Inventor： Hirotaka HAYASHI ,  Gen KOIDE

IPC: G09G3/36 ,  G02F1/1362 ,  G02F1/1368

Abstract: According to one embodiment, a display device includes a first scanning line, a second scanning line, a signal line, a capacitance line, and a pixel. The pixel includes a pixel electrode, an auxiliary electrode, a first switch, a second switch, and a third switch. The first switch is electrically connected to the signal line, the pixel electrode, and the first scanning line. The second switch is electrically connected to the auxiliary electrode, the first scanning line, and the capacitance line. The third switch is electrically connected to the signal line, the second scanning line, and the auxiliary electrode.

公开(公告)号：US20200319522A1

公开(公告)日：2020-10-08

申请号：US16910236

申请日：2020-06-24

Applicant: Japan Display Inc.

Inventor： Hirotaka HAYASHI ,  Akihiro OGAWA

IPC: G02F1/1676 ,  H01L27/12 ,  G02F1/1362 ,  G02F1/167 ,  G02F1/1343

Abstract: According to an aspect, a substrate includes an insulating base material, a pixel electrode provided on one surface side of the base material, a common electrode provided between the base material and the pixel electrode. All sides on an outer periphery of the common electrode are located inside the pixel electrode in a plan view.

公开(公告)号：US20190237032A1

公开(公告)日：2019-08-01

申请号：US16380334

申请日：2019-04-10

Applicant: Japan Display Inc.

Inventor： Masaya TAMAKI ,  Tsutomu HARADA ,  Hirotaka HAYASHI

IPC: G09G3/36

Abstract: According to one embodiment, a display device, includes a first pixel line including a first sub-pixel and a second sub-pixel, a second pixel line including a third sub-pixel and a fourth sub-pixel, and a display driver supplying video signals which cause signal polarities of signal lines adjacent to each other to be opposite to each other, without varying the polarities in one frame period, the video signals having the same polarities as each other being written to the respective sub-pixels of the first pixel line, the video signals having the polarities which are the same as each other and opposite to the polarities of the video signals written to the first pixel line, being written to the respective sub-pixels of the second pixel line.

公开(公告)号：US20150248866A1

公开(公告)日：2015-09-03

申请号：US14635389

申请日：2015-03-02

Applicant: Japan Display Inc.

Inventor： Takanori TSUNASHIMA ,  Hirotaka HAYASHI

IPC: G09G3/36 ,  G09G3/34

CPC classification number: G09G3/3607 ,  G09G3/3611 ,  G09G2300/023 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2300/0456 ,  G09G2300/0852 ,  G09G2310/08

Abstract: According to one embodiment, a display device includes a unit pixel including a first pixel, a second pixel neighboring to the first pixel in a column direction, a third pixel neighboring to the first pixel in a row direction, and a fourth pixel neighboring to the second pixel in the row direction, a scanning line extending in the row direction and electrically connected to the first to fourth pixels, and first to fourth signal lines extending in the column direction and provided at intervals therebetween in the row direction, and the first to fourth signal lines are electrically connected to the first to fourth pixels, and video signal potentials for inverted drive applied to the first and second signal lines are inverted in polarity with respect to each other, and those to the third and fourth signal lines are inverted in polarity with respect to each other.

Abstract translation: 根据一个实施例，显示装置包括：单位像素，包括第一像素，与列方向上的第一像素相邻的第二像素，与行方向上的第一像素相邻的第三像素，以及与第一像素相邻的第四像素 行方向上的第二像素，沿行方向延伸并电连接到第一至第四像素的扫描线，以及沿列方向延伸并沿行方向间隔设置的第一至第四信号线，并且第一至第四像素 第四信号线电连接到第一至第四像素，并且施加到第一和第二信号线的用于反相驱动的视频信号电位相对于彼此的极性反转，并且到第三和第四信号线的视频信号电位在 极性相对于彼此。

公开(公告)号：US20240329476A1

公开(公告)日：2024-10-03

申请号：US18735226

申请日：2024-06-06

Applicant: Japan Display Inc.

Inventor： Hirotaka HAYASHI

IPC: G02F1/1362 ,  G02F1/1339

CPC classification number: G02F1/136286 ,  G02F1/1339

Abstract: Some of a plurality of image signal lines of a display apparatus according to one embodiment includes: a plurality of bypass wiring portions (bypass wirings) arranged in a frame region so as to have both ends being connected to a plurality of extension wiring portions (extension wirings). The plurality of bypass wiring portions of the plurality of image signal lines include: a plurality of second-layer bypass wirings arranged in a second conductive layer; and a plurality of third-layer bypass wirings arranged in a third conductive layer that is different from a first conductive layer and the second conductive layer. Each of an arrangement pitch between the plurality of second-layer bypass wirings and an arrangement pitch between the plurality of third-layer bypass wirings is smaller than an arrangement pitch between the plurality of image signal lines in a display region.

公开(公告)号：US20240257780A1

公开(公告)日：2024-08-01

申请号：US18413507

申请日：2024-01-16

Applicant: Japan Display Inc.

Inventor： Hirotaka HAYASHI

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3655 ,  G09G3/2007 ,  G09G2310/08 ,  G09G2320/0252

Abstract: According to an aspect, a display device includes scan lines, signal lines, a scan circuit, a signal output circuit, pixels each having a switching element and a pixel electrode, a common electrode, and a common electrode drive circuit. In a potential reset period to reset a potential of the pixel electrode and a common potential inversion period subsequent to the potential reset period, the scan circuit supplies, to the scan lines, a drive potential to drive the switching elements, and the signal output circuit supplies, to the signal lines, an intermediate potential between a potential corresponding to a maximum gradation value and a potential corresponding to a minimum gradation value. In the common potential inversion period, the common electrode drive circuit switches the common potential between a first common potential and a second common potential higher than the first common potential.

公开(公告)号：US20230273487A1

公开(公告)日：2023-08-31

申请号：US18143624

申请日：2023-05-05

Applicant: Japan Display Inc.

Inventor： Hirotaka HAYASHI

IPC: G02F1/1362 ,  G02F1/1339

CPC classification number: G02F1/136286 ,  G02F1/1339

Abstract: Some of a plurality of image signal lines of a display apparatus according to one embodiment includes: a plurality of bypass wiring portions (bypass wirings) arranged in a frame region so as to have both ends being connected to a plurality of extension wiring portions (extension wirings). The plurality of bypass wiring portions of the plurality of image signal lines include: a plurality of second-layer bypass wirings arranged in a second conductive layer; and a plurality of third-layer bypass wirings arranged in a third conductive layer that is different from a first conductive layer and the second conductive layer. Each of an arrangement pitch between the plurality of second-layer bypass wirings and an arrangement pitch between the plurality of third-layer bypass wirings is smaller than an arrangement pitch between the plurality of image signal lines in a display region.

公开(公告)号：US20230215957A1

公开(公告)日：2023-07-06

申请号：US18181572

申请日：2023-03-10

Applicant: Japan Display Inc.

Inventor： Masataka IKEDA ,  Hirotaka HAYASHI ,  Hitoshi TANAKA

IPC: H01L29/786 ,  H01L27/12 ,  G02F1/16766 ,  G02F1/167

CPC classification number: H01L29/78696 ,  H01L27/124 ,  G02F1/16766 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/78648 ,  G02F1/167 ,  H01L29/7869 ,  H01L27/1225

Abstract: According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.