公开(公告)号：US4198694A

公开(公告)日：1980-04-15

申请号：US890172

申请日：1978-03-27

Applicant: James R. Eaton, Jr. ,  Charles G. Sodini ,  Laurence G. Walker

Inventor： James R. Eaton, Jr. ,  Charles G. Sodini ,  Laurence G. Walker

IPC: G11C11/401 ,  G11C11/35 ,  H01L21/8242 ,  H01L23/535 ,  H01L27/10 ,  H01L27/108 ,  G11C11/24 ,  G11C11/40

CPC classification number: G11C11/35 ,  H01L23/535 ,  H01L27/10805 ,  H01L2924/0002

Abstract: Each memory cell of an x-y addressable semiconductor memory includes a charge storage element serially connected with an I-O (bit) line through a pair of CCD-type transfer gates. One gate is responsive to x-addressing and the other gate to y-addressing.When an x-y address is selected only the charge storage element of the one selected memory cell communicates with the bit line.

Abstract translation: x-y可寻址半导体存储器的每个存储单元包括通过一对CCD型传输门与I-O（位）线串联连接的电荷存储元件。 一个门响应于x寻址，另一个门用于y寻址。 当仅选择x-y地址时，一个选择的存储单元的电荷存储元件与位线通信。