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公开(公告)号：US20080182490A1
公开(公告)日：2008-07-31
申请号：US11669214
申请日：2007-01-31
申请人： Rui Fang , Deepak Kulkarni , David K. Watts
发明人： Rui Fang , Deepak Kulkarni , David K. Watts
IPC分类号： B24B53/02
CPC分类号： B23H5/08
摘要： A method and system for pad conditioning in an electrochemical mechanical planarization (eCMP) tool is disclosed. A polishing pad having a pad electrode is placed onto a platen of the eCMP tool. A conditioning disk, having a second electrode is placed on the polishing pad, such that the pad electrode and conditioning disk form an electrode pair. An electric potential is established between the conditioning disk and the pad electrode. This causes debris from the polishing pad to become ionized, and attracted to the conditioning disk. The conditioning disk is then removed from the eCMP tool, allowing the eCMP tool to resume operation on normal semiconductor wafers.
摘要翻译： 公开了一种用于电化学机械平面化（eCMP）工具中的垫调节的方法和系统。 具有焊盘电极的抛光垫被放置在eCMP工具的压板上。 具有第二电极的调节盘被放置在抛光垫上，使得焊盘电极和调节盘形成电极对。 在调节盘和焊盘电极之间建立电位。 这导致来自抛光垫的碎屑被电离，并被吸引到调节盘。 然后将调理盘从eCMP工具中取出，允许eCMP工具恢复正常半导体晶片的操作。
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12.发明授权Method of making a semiconductor device using chemical-mechanical polishing having a combination-step process 失效使用具有组合步骤工艺的化学机械抛光制造半导体器件的方法
公开(公告)号：US5985748A
公开(公告)日：1999-11-16
申请号：US980782
申请日：1997-12-01
IPC分类号： H01L21/321 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/3212 , H01L21/7684
摘要： A method of chemical-mechanical polishing of a semiconductor device utilizes a combination of polishing steps, including a first step using a first slurry containing an abrasive component (i.e., mechanical component) and a chemical component (i.e., chemical reactants), and a second polishing step using a second slurry having a reduced amount of the abrasive component. The method is carried out with respect to metal (39), such as copper, deposited on a dielectric layer (34) and the first polishing step is stopped before the entirety of the metal overlying the dielectric layer is removed. In one embodiment, the second slurry has no abrasive component.
摘要翻译： 半导体器件的化学机械抛光的方法利用抛光步骤的组合，包括使用包含磨料组分（即机械部件）和化学组分（即化学反应物）的第一浆料的第一步骤，以及第二步骤 抛光步骤使用具有减少量的磨料组分的第二浆料。 该方法相对于沉积在电介质层（34）上的金属（39）如铜进行，并且在去除覆盖在电介质层上的整个金属之前停止第一抛光步骤。 在一个实施方案中，第二浆料没有磨料组分。
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13.发明授权Recycling of electrochemical-mechanical planarization (ECMP) slurries/electrolytes 有权电化学机械平面化（ECMP）浆料/电解质的回收公开(公告)号：US07820051B2
公开(公告)日：2010-10-26
申请号：US11678089
申请日：2007-02-23
申请人： Rui Fang , Deepak Kulkarni , David K. Watts
发明人： Rui Fang , Deepak Kulkarni , David K. Watts
IPC分类号： B01D11/00
CPC分类号： C22B7/006 , C22B3/42 , Y02P10/234
摘要： A method, process and system for the recycling of electrochemical-mechanical planarization slurries/electrolytes as they are used in the back end of line of the semiconductor wafer manufacturing process is disclosed. The method, process and system includes with the removal of metal ions from slurries using ion exchange media and/or electrochemical deposition.
摘要翻译： 公开了一种用于电化学 - 机械平面化浆料/电解质的再循环的方法，方法和系统，因为它们用于半导体晶片制造工艺的后端。 该方法，方法和系统包括使用离子交换介质和/或电化学沉积从浆料中除去金属离子。
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公开(公告)号：US07544609B2
公开(公告)日：2009-06-09
申请号：US11673276
申请日：2007-02-09
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/7684 , H01L21/76877
摘要： A method for integrating cap liner formation in back-end-of-line (BEOL) processing of a semiconductor device includes forming a trench structure within an insulating layer of the semiconductor device, depositing a first liner material over a top surface of the insulating layer, including sidewall and bottom surfaces of the trench, and partially filling the trench with a wiring metal material to a height corresponding to a final intended line height. A second liner material is over the wiring metal material, and a sacrificial fill material is formed over the second liner material. The sacrificial fill is planarized down to the level of the second liner material over the wiring metal material partially filling the trench, wherein a remaining portion of the second liner material defines a cap liner of the wiring metal.
摘要翻译： 一种用于在半导体器件的后端行（BEOL）处理中集成帽衬层形成的方法包括在半导体器件的绝缘层内形成沟槽结构，在绝缘层的顶表面上沉积第一衬里材料 ，包括沟槽的侧壁和底表面，并且用布线金属材料将沟槽部分地填充到与最终预定的线高度相对应的高度。 第二衬里材料在布线金属材料上方，并且在第二衬里材料上形成牺牲填充材料。 将牺牲填充物平坦化到部分填充沟槽的布线金属材料上的第二衬垫材料的水平面上，其中第二衬垫材料的剩余部分限定了布线金属的盖衬垫。
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公开(公告)号：US20080194099A1
公开(公告)日：2008-08-14
申请号：US11673276
申请日：2007-02-09
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/7684 , H01L21/76877
摘要： A method for integrating cap liner formation in back-end-of-line (BEOL) processing of a semiconductor device includes forming a trench structure within an insulating layer of the semiconductor device, depositing a first liner material over a top surface of the insulating layer, including sidewall and bottom surfaces of the trench, and partially filling the trench with a wiring metal material to a height corresponding to a final intended line height. A second liner material is over the wiring metal material, and a sacrificial fill material is formed over the second liner material. The sacrificial fill is planarized down to the level of the second liner material over the wiring metal material partially filling the trench, wherein a remaining portion of the second liner material defines a cap liner of the wiring metal.
摘要翻译： 一种用于在半导体器件的后端行（BEOL）处理中集成帽衬层形成的方法包括在半导体器件的绝缘层内形成沟槽结构，在绝缘层的顶表面上沉积第一衬里材料 ，包括沟槽的侧壁和底表面，并且用布线金属材料将沟槽部分地填充到与最终预定的线高度相对应的高度。 第二衬里材料在布线金属材料上方，并且在第二衬里材料上形成牺牲填充材料。 将牺牲填充物平坦化到部分填充沟槽的布线金属材料上的第二衬垫材料的水平面上，其中第二衬垫材料的剩余部分限定了布线金属的盖衬垫。
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