公开(公告)号：US20130005147A1

公开(公告)日：2013-01-03

申请号：US13170621

申请日：2011-06-28

申请人： Matthew S. Angyal ,  Oluwafemi O. Ogunsola ,  Hakeem B. Akinmade-Yusuff

发明人： Matthew S. Angyal ,  Oluwafemi O. Ogunsola ,  Hakeem B. Akinmade-Yusuff

IPC分类号： H01L21/306 ,  H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76805 ,  H01L21/76816

摘要： A method including forming an organic polymer layer (OPL) on a substrate; forming a patterned photoresist layer having a first opening and a second opening over the OPL, the second opening wider than the first opening; performing a first reactive ion etch (RIE) to form a first trench and a second trench in the organic layer, the second trench wider than the first trench, the first trench extending into but not through the organic polymer layer, the second trench extending through the OPL to the substrate, the first RIE forming a first polymer layer on sidewalls of the first trench and a second polymer layer on sidewalls of the second trench, the second polymer layer thicker than the first polymer layer; and performing a second RIE to extend the first trench through the OPL to the substrate, the second RIE removing the second polymer layer from sidewalls of the second trench.

摘要翻译： 一种包括在基材上形成有机聚合物层（OPL）的方法; 在所述OPL上形成具有第一开口和第二开口的图案化光致抗蚀剂层，所述第二开口比所述第一开口更宽; 执行第一反应离子蚀刻（RIE）以在有机层中形成第一沟槽和第二沟槽，第二沟槽比第一沟槽宽，第一沟槽延伸到但不穿过有机聚合物层，第二沟槽延伸穿过 所述第一聚合物层在所述第一沟槽的侧壁上形成第一聚合物层，在所述第二沟槽的侧壁上形成第二聚合物层，所述第二聚合物层比所述第一聚合物层厚; 以及执行第二RIE以将所述第一沟槽通过所述OPL延伸到所述衬底，所述第二RIE从所述第二沟槽的侧壁移除所述第二聚合物层。

公开(公告)号：US08450212B2

公开(公告)日：2013-05-28

申请号：US13170621

申请日：2011-06-28

申请人： Matthew S. Angyal ,  Oluwafemi O. Ogunsola ,  Hakeem B. Akinmade-Yusuff

发明人： Matthew S. Angyal ,  Oluwafemi O. Ogunsola ,  Hakeem B. Akinmade-Yusuff

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76805 ,  H01L21/76816

摘要： A method including forming an organic polymer layer (OPL) on a substrate; forming a patterned photoresist layer having a first opening and a second opening over the OPL, the second opening wider than the first opening; performing a first reactive ion etch (RIE) to form a first trench and a second trench in the organic layer, the second trench wider than the first trench, the first trench extending into but not through the organic polymer layer, the second trench extending through the OPL to the substrate, the first RIE forming a first polymer layer on sidewalls of the first trench and a second polymer layer on sidewalls of the second trench, the second polymer layer thicker than the first polymer layer; and performing a second RIE to extend the first trench through the OPL to the substrate, the second RIE removing the second polymer layer from sidewalls of the second trench.

摘要翻译： 一种包括在基材上形成有机聚合物层（OPL）的方法; 在所述OPL上形成具有第一开口和第二开口的图案化光致抗蚀剂层，所述第二开口比所述第一开口更宽; 执行第一反应离子蚀刻（RIE）以在有机层中形成第一沟槽和第二沟槽，第二沟槽比第一沟槽宽，第一沟槽延伸到但不穿过有机聚合物层，第二沟槽延伸穿过 所述第一聚合物层在所述第一沟槽的侧壁上形成第一聚合物层，在所述第二沟槽的侧壁上形成第二聚合物层，所述第二聚合物层比所述第一聚合物层厚; 以及执行第二RIE以将所述第一沟槽通过所述OPL延伸到所述衬底，所述第二RIE从所述第二沟槽的侧壁移除所述第二聚合物层。

公开(公告)号：US20100200960A1

公开(公告)日：2010-08-12

申请号：US12689479

申请日：2010-01-19

申请人： Matthew S. Angyal ,  Lawrence A. Clevenger ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Shaoning Yao

发明人： Matthew S. Angyal ,  Lawrence A. Clevenger ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Shaoning Yao

IPC分类号： H01L23/544 ,  H01L21/302

CPC分类号： H01L23/585 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.

摘要翻译： 形成在半导体衬底的接触电平下方的深沟槽作为裂纹，在晶片的管芯区域或划线区域中起作用，并且可以设置成距它们旨在保护的器件的距离增加的行，并且可以位于 在互连堆叠层中的格子工作裂纹结构下。 深沟槽可以保持未填充，或者可以用介电材料或导体填充。 深沟槽可以具有大约1微米至100微米的衬底的深度和约10nm至10微米的宽度。

公开(公告)号：US06967158B2

公开(公告)日：2005-11-22

申请号：US10384398

申请日：2003-03-07

申请人： Yuri Solomentsev ,  Matthew S. Angyal ,  Errol Todd Ryan ,  Susan Gee-Young Kim

发明人： Yuri Solomentsev ,  Matthew S. Angyal ,  Errol Todd Ryan ,  Susan Gee-Young Kim

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/3212 ,  H01L21/76829 ,  H01L21/7684

摘要： The present invention provides a method for forming a low-k dielectric structure on a substrate 10 that includes depositing, upon the substrate, a dielectric layer 12. A multi-film cap layer 18 is deposited upon the dielectric layer. The multi-film cap layer includes first 181 and second 182 films, with the second film being disposed between the dielectric layer and the first film. The first film typically has a removal rate associated therewith that is less than the removal rate associated with the second film. A deposition layer 20 is deposited upon the multi-film cap layer and subsequently removed. The properties of the multi-film cap layer are selected so as to prevent the dielectric layer from being exposed/removed during removal of the deposition film. In this manner, a deposition layer, having variable rates of removal, such as copper, may be planarized without damaging the underlying dielectric layer.

摘要翻译： 本发明提供了一种用于在衬底10上形成低k电介质结构的方法，该方法包括在衬底上沉积介电层12.多层覆盖层18沉积在电介质层上。 多层膜层包括第一和第二膜182，其中第二膜设置在电介质层和第一膜之间。 第一膜通常具有与其相关联的去除速率小于与第二膜相关联的去除速率。 沉积层20沉积在多膜覆盖层上并随后除去。 选择多层盖层的性质，以防止在去除沉积膜期间电介质层被曝光/去除。 以这种方式，可以平坦化具有可变迁移速率（例如铜）的沉积层，而不会损坏下面的介电层。

公开(公告)号：US07214608B2

公开(公告)日：2007-05-08

申请号：US10710706

申请日：2004-07-29

申请人： Matthew S. Angyal ,  Peter E. Biolsi ,  Lawrence A. Clevenger ,  Habib Hichri ,  Bernd E. Kastenmeier ,  Michael W. Lane ,  Jeffrey R. Marino ,  Vincent J. McGahay ,  Theodorus E. Standaert

发明人： Matthew S. Angyal ,  Peter E. Biolsi ,  Lawrence A. Clevenger ,  Habib Hichri ,  Bernd E. Kastenmeier ,  Michael W. Lane ,  Jeffrey R. Marino ,  Vincent J. McGahay ,  Theodorus E. Standaert

IPC分类号： H01L21/4763

CPC分类号： H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76844

摘要： Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.

摘要翻译： 在蚀刻步骤之后密封有机ILD层和金属层的方法。 该方法包括蚀刻穿过ILD层并留下下面的金属层帽的剩余部分，将该装置保持在惰性气体中，并将​​衬垫的至少一部分沉积到开口中以密封ILD层和金属层。 随后的处理可以包括通过蚀刻穿过衬套的一部分和盖层的剩余部分以及沉积金属来形成通孔。

公开(公告)号：US08237246B2

公开(公告)日：2012-08-07

申请号：US12689479

申请日：2010-01-19

申请人： Matthew S. Angyal ,  Lawrence A. Clevenger ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Shaoning Yao

发明人： Matthew S. Angyal ,  Lawrence A. Clevenger ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Shaoning Yao

IPC分类号： H01L23/544

CPC分类号： H01L23/585 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.

摘要翻译： 形成在半导体衬底的接触电平下方的深沟槽作为裂纹，在晶片的管芯区域或划线区域中起作用，并且可以设置成距它们旨在保护的器件的距离增加的行，并且可以位于 在互连堆叠层中的格子工作裂纹结构下。 深沟槽可以保持未填充，或者可以用介电材料或导体填充。 深沟槽可以具有大约1微米至100微米的衬底的深度和约10nm至10微米的宽度。

公开(公告)号：US08188574B2

公开(公告)日：2012-05-29

申请号：US12704567

申请日：2010-02-12

申请人： Matthew S. Angyal ,  Mahender Kumar ,  Effendi Leobandung ,  Jay W. Strane

发明人： Matthew S. Angyal ,  Mahender Kumar ,  Effendi Leobandung ,  Jay W. Strane

IPC分类号： H01L29/72

CPC分类号： H01L23/585 ,  H01L21/76264 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip.

摘要翻译： 微电子元件，例如具有通过掩埋氧化物（BOX）层与大块单晶硅层分离的绝缘体上硅层（“SOI层”）的半导体芯片，其中裂纹阻挡层在第一横向至少延伸至少 通常平行于芯片的边缘以限定将芯片内的芯片的有源部分与芯片的周边部分分开的环状势垒。 裂纹停止件可以包括与BOX层上方的芯片的硅部分接触的第一裂纹阻挡环; 第一裂纹阻挡环可以在第一横向方向上连续延伸以围绕芯片的有效部分。 包括GR接触环的保护环（“GR”）可以向下延伸穿过SOI层和BOX层以导电接触大块单晶硅区域，GR接触环至少大致平行于第一裂纹阻挡环延伸以包围 芯片的有效部分。 在第一横向方向上连续延伸的连续金属环可以围绕芯片的有效部分，这种金属环将GR接触环与第一裂纹阻止环连接，使得金属线和GR接触环形成连续的密封，防止移动 离子在芯片的外围和有源部分之间移动。

公开(公告)号：US20100200958A1

公开(公告)日：2010-08-12

申请号：US12704567

申请日：2010-02-12

申请人： Matthew S. Angyal ,  Mahender Kumar ,  Effendi Leobandung ,  Jay W. Strane

发明人： Matthew S. Angyal ,  Mahender Kumar ,  Effendi Leobandung ,  Jay W. Strane

IPC分类号： H01L23/00 ,  H01L21/762

CPC分类号： H01L23/585 ,  H01L21/76264 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip.

摘要翻译： 微电子元件，例如具有通过掩埋氧化物（BOX）层与大块单晶硅层分离的绝缘体上硅层（“SOI层”）的半导体芯片，其中裂纹阻挡层在第一横向至少延伸至少 通常平行于芯片的边缘以限定将芯片内的芯片的有源部分与芯片的周边部分分开的环状势垒。 裂纹停止件可以包括与BOX层上方的芯片的硅部分接触的第一裂纹阻挡环; 第一裂纹阻挡环可以在第一横向方向上连续延伸以围绕芯片的有效部分。 包括GR接触环的保护环（“GR”）可以向下延伸穿过SOI层和BOX层以导电接触大块单晶硅区域，GR接触环至少大致平行于第一裂纹阻挡环延伸以包围 芯片的有效部分。 在第一横向方向上连续延伸的连续金属环可以围绕芯片的有效部分，这种金属环将GR接触环与第一裂纹阻止环连接，使得金属线和GR接触环形成连续的密封，防止移动 离子在芯片的外围和有源部分之间移动。

公开(公告)号：US06917108B2

公开(公告)日：2005-07-12

申请号：US10294139

申请日：2002-11-14

申请人： John A. Fitzsimmons ,  Stephen E. Greco ,  Jia Lee ,  Stephen M. Gates ,  Terry Spooner ,  Matthew S. Angyal ,  Habib Hichri ,  Theordorus E. Standaert ,  Glenn A. Biery

发明人： John A. Fitzsimmons ,  Stephen E. Greco ,  Jia Lee ,  Stephen M. Gates ,  Terry Spooner ,  Matthew S. Angyal ,  Habib Hichri ,  Theordorus E. Standaert ,  Glenn A. Biery

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

公开(公告)号：US07544609B2

公开(公告)日：2009-06-09

申请号：US11673276

申请日：2007-02-09

申请人： Matthew S. Angyal ,  Habib Hichri ,  Christopher J. Penny ,  David K. Watts

发明人： Matthew S. Angyal ,  Habib Hichri ,  Christopher J. Penny ,  David K. Watts

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/7684 ,  H01L21/76877

摘要： A method for integrating cap liner formation in back-end-of-line (BEOL) processing of a semiconductor device includes forming a trench structure within an insulating layer of the semiconductor device, depositing a first liner material over a top surface of the insulating layer, including sidewall and bottom surfaces of the trench, and partially filling the trench with a wiring metal material to a height corresponding to a final intended line height. A second liner material is over the wiring metal material, and a sacrificial fill material is formed over the second liner material. The sacrificial fill is planarized down to the level of the second liner material over the wiring metal material partially filling the trench, wherein a remaining portion of the second liner material defines a cap liner of the wiring metal.

摘要翻译： 一种用于在半导体器件的后端行（BEOL）处理中集成帽衬层形成的方法包括在半导体器件的绝缘层内形成沟槽结构，在绝缘层的顶表面上沉积第一衬里材料 ，包括沟槽的侧壁和底表面，并且用布线金属材料将沟槽部分地填充到与最终预定的线高度相对应的高度。 第二衬里材料在布线金属材料上方，并且在第二衬里材料上形成牺牲填充材料。 将牺牲填充物平坦化到部分填充沟槽的布线金属材料上的第二衬垫材料的水平面上，其中第二衬垫材料的剩余部分限定了布线金属的盖衬垫。