公开(公告)号：US20120185231A1

公开(公告)日：2012-07-19

申请号：US13008921

申请日：2011-01-19

申请人： Chen-Kang LO ,  Li-Chun Chen ,  Meng-Huan Wu ,  Ren-Song Tsay

发明人： Chen-Kang LO ,  Li-Chun Chen ,  Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F2217/68

摘要： The present invention discloses a cycle-count-accurate (CCA) processor modeling, which can achieve high simulation speeds while maintaining timing accuracy of the system simulation. The CCA processor modeling includes a pipeline subsystem model and a cache subsystem model with accurate cycle with accurate cycle count information and guarantees accurate timing and functional behaviors on processor interface. The CCA processor modeling further includes a branch predictor and a bus interface (BIF) to predict the branch of pipeline execution behavior (PEB) and to simulate the data accesses between the processor and the external components via an external bus, respectively. The experimental results show that the CCA processor modeling performs 50 times faster than the corresponding Cycle-accurate (CA) model while providing the same cycle count information as the target RTL model.

摘要翻译： 本发明公开了一种循环计数精确（CCA）处理器建模，可以实现高仿真速度，同时保持系统仿真的定时精度。 CCA处理器建模包括管道子系统模型和具有精确周期的缓存子系统模型，具有精确的周期计数信息，并保证处理器接口上的精确时序和功能行为。 CCA处理器建模还包括分支预测器和总线接口（BIF），以预测流水线执行行为（PEB）的分支，并分别通过外部总线模拟处理器与外部组件之间的数据访问。 实验结果表明，CCA处理器建模比相应的周期精确（CA）模型快50倍，同时提供与目标RTL模型相同的周期计数信息。

公开(公告)号：US08549468B2

公开(公告)日：2013-10-01

申请号：US12701810

申请日：2010-02-08

申请人： Meng-Huan Wu ,  Ren-Song Tsay

发明人： Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06F9/44

CPC分类号： G06F8/53

摘要： The present invention discloses a system for generating a software TLM model, comprising a processing unit; a compiler coupled to the processing unit to generate target binary codes of a target software; a decompiler coupled to the processing unit to decompile the target binary codes into high level codes, for example C or C++ codes, to generate a functional model of the target software, wherein the functional model includes a plurality of basic blocks; an execution time calculating module coupled to the processing unit to calculate overall execution time of the plurality of the basic blocks of the functional model; a sync point identifying module coupled to the processing unit to identify sync points of the software transaction-level modeling model; and a time annotating module coupled to the processing unit to annotate the overall execution time of the basic blocks and the sync points into the functional model to obtain the software transaction-level modeling model.

摘要翻译： 本发明公开了一种生成软件TLM模型的系统，包括处理单元; 耦合到所述处理单元以生成目标软件的目标二进制代码的编译器; 反编译器，其耦合到所述处理单元以将所述目标二进制代码反编译为高级代码，例如C或C ++代码，以生成所述目标软件的功能模型，其中所述功能模型包括多个基本块; 执行时间计算模块，耦合到所述处理单元，以计算所述功能模型的所述多个基本块的总执行时间; 耦合到所述处理单元的同步点识别模块，以识别所述软件交易级建模模型的同步点; 以及耦合到处理单元的时间注释模块，以将基本块和同步点的总体执行时间注释到功能模型中以获得软件事务级建模模型。

公开(公告)号：US20120233410A1

公开(公告)日：2012-09-13

申请号：US13046743

申请日：2011-03-13

申请人： Cheng-Yang FU ,  Meng-Huan Wu ,  Ren-Song Tsay

发明人： Cheng-Yang FU ,  Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0837

摘要： The present invention discloses a shared-variable-based (SVB) approach for fast and accurate multi-core cache coherence simulation. While the intuitive, conventional approach, synchronizing at either every cycle or memory access, gives accurate simulation results, it has poor performance due to huge simulation overloads. In the present invention, timing synchronization is only needed before shared variable accesses in order to maintain accuracy while improving the efficiency in the proposed shared-variable-based approach.

摘要翻译： 本发明公开了一种用于快速准确的多核高速缓存一致性模拟的共享变量（SVB）方法。 虽然直观的常规方法，在每个周期或存储器访问同步，给出精确的模拟结果，由于巨大的模拟过载，它的性能不佳。 在本发明中，仅在共享变量访问之前需要定时同步，以便在提出基于共享变量的方法中提高效率的同时保持准确性。

公开(公告)号：US20120197625A1

公开(公告)日：2012-08-02

申请号：US13016933

申请日：2011-01-28

申请人： Peng-Chih WANG ,  Meng-Huan Wu ,  Ren-Song Tsay

发明人： Peng-Chih WANG ,  Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06F9/45

CPC分类号： G06F9/485 ,  G06F17/5022

摘要： In the present disclosure, the DOM approach for the simulation of OS preemptive scheduling has presented and demonstrated. By maintaining the data-dependency between the software tasks, and guaranteeing the order of shared variable accesses, it can accurately simulate the preemption effect. Moreover, the proposed DOM OS model is implemented to enable preemptive scheduling in SystemC.

摘要翻译： 在本公开中，用于模拟OS抢占式调度的DOM方法已经呈现并展示出来。 通过维护软件任务之间的数据依赖关系，保证共享变量访问的顺序，可以准确模拟抢占效果。 此外，提出的DOM OS模型被实现为在SystemC中启用抢占式调度。