公开(公告)号：US08352924B2

公开(公告)日：2013-01-08

申请号：US12588324

申请日：2009-10-13

申请人： Meng-Huan Wu ,  Cheng-Yang Fu ,  Peng-Chih Wang ,  Ren-Song Tsay

发明人： Meng-Huan Wu ,  Cheng-Yang Fu ,  Peng-Chih Wang ,  Ren-Song Tsay

IPC分类号： G06F9/45

CPC分类号： G06F17/5022 ,  G06F8/53 ,  G06F9/4552 ,  G06F2217/68

摘要： The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation.

摘要翻译： 本发明公开了一种多核指令集仿真方法。 所提出的方法识别共享数据段和不同核心之间的依赖关系，从而有效减少同步点数量，降低同步开销，从而允许更多地执行多核指令集仿真，同时确保仿真结果 是准确的 此外，本发明还公开了一种用于多核指令集仿真的装置。

公开(公告)号：US20120197625A1

公开(公告)日：2012-08-02

申请号：US13016933

申请日：2011-01-28

申请人： Peng-Chih WANG ,  Meng-Huan Wu ,  Ren-Song Tsay

发明人： Peng-Chih WANG ,  Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06F9/45

CPC分类号： G06F9/485 ,  G06F17/5022

摘要： In the present disclosure, the DOM approach for the simulation of OS preemptive scheduling has presented and demonstrated. By maintaining the data-dependency between the software tasks, and guaranteeing the order of shared variable accesses, it can accurately simulate the preemption effect. Moreover, the proposed DOM OS model is implemented to enable preemptive scheduling in SystemC.

摘要翻译： 在本公开中，用于模拟OS抢占式调度的DOM方法已经呈现并展示出来。 通过维护软件任务之间的数据依赖关系，保证共享变量访问的顺序，可以准确模拟抢占效果。 此外，提出的DOM OS模型被实现为在SystemC中启用抢占式调度。

公开(公告)号：US20100269103A1

公开(公告)日：2010-10-21

申请号：US12588324

申请日：2009-10-13

申请人： Meng-Huan Wu ,  Cheng-Yang Fu ,  Peng-Chih Wang ,  Ren-Song Tsay

发明人： Meng-Huan Wu ,  Cheng-Yang Fu ,  Peng-Chih Wang ,  Ren-Song Tsay

IPC分类号： G06F9/45

CPC分类号： G06F17/5022 ,  G06F8/53 ,  G06F9/4552 ,  G06F2217/68

摘要： The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation.

摘要翻译： 本发明公开了一种多核指令集仿真方法。 所提出的方法识别共享数据段和不同核心之间的依赖关系，从而有效减少同步点数量，降低同步开销，从而允许更多地执行多核指令集仿真，同时确保仿真结果 是准确的 此外，本发明还公开了一种用于多核指令集仿真的装置。

公开(公告)号：US20110197174A1

公开(公告)日：2011-08-11

申请号：US12701810

申请日：2010-02-08

申请人： Meng-Huan WU ,  Ren-Song Tsay

发明人： Meng-Huan WU ,  Ren-Song Tsay

IPC分类号： G06F9/45

CPC分类号： G06F8/53

摘要： The present invention discloses a system for generating a software TLM model, comprising a processing unit; a compiler coupled to the processing unit to generate target binary codes of a target software; a decompiler coupled to the processing unit to decompile the target binary codes into high level codes, for example C or C++ codes, to generate a functional model of the target software, wherein the functional model includes a plurality of basic blocks; an execution time calculating module coupled to the processing unit to calculate overall execution time of the plurality of the basic blocks of the functional model; a sync point identifying module coupled to the processing unit to identify sync points of the software transaction-level modeling model; and a time annotating module coupled to the processing unit to annotate the overall execution time of the basic blocks and the sync points into the functional model to obtain the software transaction-level modeling model.

摘要翻译： 本发明公开了一种生成软件TLM模型的系统，包括处理单元; 耦合到所述处理单元以生成目标软件的目标二进制代码的编译器; 反编译器，其耦合到所述处理单元以将所述目标二进制代码反编译为高级代码，例如C或C ++代码，以生成所述目标软件的功能模型，其中所述功能模型包括多个基本块; 执行时间计算模块，耦合到所述处理单元，以计算所述功能模型的所述多个基本块的总执行时间; 耦合到所述处理单元的同步点识别模块，以识别所述软件交易级建模模型的同步点; 以及耦合到处理单元的时间注释模块，以将基本块和同步点的总体执行时间注释到功能模型中以获得软件事务级建模模型。

公开(公告)号：US20120191441A1

公开(公告)日：2012-07-26

申请号：US13011942

申请日：2011-01-24

申请人： Meng-Huan Wu ,  Ren-Song Tsay

发明人： Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06F9/455

CPC分类号： G06F17/5022 ,  G06F9/52 ,  G06F2217/68

摘要： The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized. The distributed scheduling with the present invention's prediction method significantly shortens the waiting time which an ISS spends on synchronization

摘要翻译： 本发明公开了一种用于多核指令集仿真的高并行同步方法。 所提出的方法利用并行编译的MCISS的新的分布式调度机制。 所提出的方法可以增强MCISS的并行性，从而可以有效利用多核主机的计算能力。 利用本发明的预测方法的分布式调度大大缩短了ISS花费在同步上的等待时间

公开(公告)号：US20120185231A1

公开(公告)日：2012-07-19

申请号：US13008921

申请日：2011-01-19

申请人： Chen-Kang LO ,  Li-Chun Chen ,  Meng-Huan Wu ,  Ren-Song Tsay

发明人： Chen-Kang LO ,  Li-Chun Chen ,  Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F2217/68

摘要： The present invention discloses a cycle-count-accurate (CCA) processor modeling, which can achieve high simulation speeds while maintaining timing accuracy of the system simulation. The CCA processor modeling includes a pipeline subsystem model and a cache subsystem model with accurate cycle with accurate cycle count information and guarantees accurate timing and functional behaviors on processor interface. The CCA processor modeling further includes a branch predictor and a bus interface (BIF) to predict the branch of pipeline execution behavior (PEB) and to simulate the data accesses between the processor and the external components via an external bus, respectively. The experimental results show that the CCA processor modeling performs 50 times faster than the corresponding Cycle-accurate (CA) model while providing the same cycle count information as the target RTL model.

摘要翻译： 本发明公开了一种循环计数精确（CCA）处理器建模，可以实现高仿真速度，同时保持系统仿真的定时精度。 CCA处理器建模包括管道子系统模型和具有精确周期的缓存子系统模型，具有精确的周期计数信息，并保证处理器接口上的精确时序和功能行为。 CCA处理器建模还包括分支预测器和总线接口（BIF），以预测流水线执行行为（PEB）的分支，并分别通过外部总线模拟处理器与外部组件之间的数据访问。 实验结果表明，CCA处理器建模比相应的周期精确（CA）模型快50倍，同时提供与目标RTL模型相同的周期计数信息。

公开(公告)号：US08549468B2

公开(公告)日：2013-10-01

申请号：US12701810

申请日：2010-02-08

申请人： Meng-Huan Wu ,  Ren-Song Tsay

发明人： Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06F9/44

CPC分类号： G06F8/53

摘要： The present invention discloses a system for generating a software TLM model, comprising a processing unit; a compiler coupled to the processing unit to generate target binary codes of a target software; a decompiler coupled to the processing unit to decompile the target binary codes into high level codes, for example C or C++ codes, to generate a functional model of the target software, wherein the functional model includes a plurality of basic blocks; an execution time calculating module coupled to the processing unit to calculate overall execution time of the plurality of the basic blocks of the functional model; a sync point identifying module coupled to the processing unit to identify sync points of the software transaction-level modeling model; and a time annotating module coupled to the processing unit to annotate the overall execution time of the basic blocks and the sync points into the functional model to obtain the software transaction-level modeling model.

摘要翻译： 本发明公开了一种生成软件TLM模型的系统，包括处理单元; 耦合到所述处理单元以生成目标软件的目标二进制代码的编译器; 反编译器，其耦合到所述处理单元以将所述目标二进制代码反编译为高级代码，例如C或C ++代码，以生成所述目标软件的功能模型，其中所述功能模型包括多个基本块; 执行时间计算模块，耦合到所述处理单元，以计算所述功能模型的所述多个基本块的总执行时间; 耦合到所述处理单元的同步点识别模块，以识别所述软件交易级建模模型的同步点; 以及耦合到处理单元的时间注释模块，以将基本块和同步点的总体执行时间注释到功能模型中以获得软件事务级建模模型。

公开(公告)号：US20120233410A1

公开(公告)日：2012-09-13

申请号：US13046743

申请日：2011-03-13

申请人： Cheng-Yang FU ,  Meng-Huan Wu ,  Ren-Song Tsay

发明人： Cheng-Yang FU ,  Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0837

摘要： The present invention discloses a shared-variable-based (SVB) approach for fast and accurate multi-core cache coherence simulation. While the intuitive, conventional approach, synchronizing at either every cycle or memory access, gives accurate simulation results, it has poor performance due to huge simulation overloads. In the present invention, timing synchronization is only needed before shared variable accesses in order to maintain accuracy while improving the efficiency in the proposed shared-variable-based approach.

摘要翻译： 本发明公开了一种用于快速准确的多核高速缓存一致性模拟的共享变量（SVB）方法。 虽然直观的常规方法，在每个周期或存储器访问同步，给出精确的模拟结果，由于巨大的模拟过载，它的性能不佳。 在本发明中，仅在共享变量访问之前需要定时同步，以便在提出基于共享变量的方法中提高效率的同时保持准确性。

公开(公告)号：US20110218791A1

公开(公告)日：2011-09-08

申请号：US12716446

申请日：2010-03-03

申请人： Chien-Min LEE ,  Chen-Kang Lo ,  Meng-Huan Wu ,  Ren-Song Tsay

发明人： Chien-Min LEE ,  Chen-Kang Lo ,  Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06G7/62

CPC分类号： G06G7/62

摘要： The present invention provides a method for simulating processor power consumption, the method comprises: simulating a simulated processor; utilizing a power analysis model to analyze the simulated processor's execution of at least one fragment of a program, for generating power analysis of a plurality of basic blocks of the at least one fragment; computing at least one power correction factor between the plurality of basic block; utilizing a processing apparatus to generate a simulation model with power annotation based on the power analysis and the at least one power correction factor; and predicting power consumption of the simulated processor based on the simulation model with power annotation.

摘要翻译： 本发明提供了一种用于模拟处理器功耗的方法，所述方法包括：模拟模拟处理器; 利用功率分析模型来分析所述模拟处理器对程序的至少一个片段的执行，以产生所述至少一个片段的多个基本块的功率分析; 计算所述多个基本块之间的至少一个功率校正因子; 利用处理装置基于功率分析和至少一个功率校正因子来生成具有功率注释的仿真模型; 并基于具有功率注释的仿真模型预测模拟处理器的功耗。

公开(公告)号：US20130179864A1

公开(公告)日：2013-07-11

申请号：US13455659

申请日：2012-04-25

申请人： Yi-Shan Lu ,  Hsien-Lun Pai ,  Meng-Huan Wu ,  Ren-Song Tsay

发明人： Yi-Shan Lu ,  Hsien-Lun Pai ,  Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06F9/44

CPC分类号： G06F9/524

摘要： A deadlock free synchronization synthesizer for must-happen-before relations in at least two parallel programs or at least two threads each having multiple code segments has an input device to specify a synchronization point to involving code segments for each parallel program or thread and must-happen-before relations to the synchronization point, an analyzing module connected to the input device to detect existence of a deadlock in the parallel programs by using the must-happen-before relations, and a synthesizing module connected to the analyzing module to synthesize a practice code corresponding to the parallel programs if the deadlock existence detection is negative.

摘要翻译： 用于至少两个并行程序中的必须发生关系的无死锁同步合成器或至少两个具有多个代码段的线程具有用于指定同步点以涉及每个并行程序或线程的代码段的输入设备， 发生在与同步点之间的关系之前，连接到输入设备的分析模块通过使用必须事先关系来检测并行程序中的死锁的存在，以及连接到分析模块以合成实践的合成模块 如果死锁存在检测为负，则对应于并行程序的代码。