公开(公告)号：US20080066037A1

公开(公告)日：2008-03-13

申请号：US11531322

申请日：2006-09-13

申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of force directed placement programming is presented. The method includes sorting objects of a netlist for placement by magnitude of their spreading force and selecting a plurality of the objects. The method further includes waiving (or nullifying) the spreading force for the selected objects in a subsequent non-linear program solver step of the force directed placement program. The positions of the objects after the subsequent non-linear program solver step are based only on their connections to other objects in the netlist. The selected objects no longer retain their relative ordering as obtained during a previous non-linear program solve step of the force directed placement program. An alternative method of force directed placement programming is also present, which includes identifying objects from a netlist for placement that have a very high spreading force magnitude. The method further includes controlling the spreading force magnitude for the objects identified in the force directed placement programming to reduce wirelength in a chip design without sacrificing spreading of the objects.

摘要翻译： 提出了一种强制定向布置程序的方法。 该方法包括对网表的对象进行排序，以便按照其展开力的大小进行放置并选择多个对象。 该方法还包括在力定向放置程序的随后非线性程序解算器步骤中放弃（或消除）所选对象的展开力。 在后续非线性程序求解器步骤之后的对象的位置仅基于它们与网表中其他对象的连接。 所选择的对象不再保留在力定向放置程序的先前非线性程序解决步骤中获得的相对排序。 还存在一种替代的力定向放置编程的方法，其包括从具有非常高的铺展力量级的用于放置的网表识别对象。 该方法还包括控制在力定向放置编程中识别的物体的展开力大小以减少芯片设计中的线长度，而不牺牲物体的扩展。

公开(公告)号：US20080047732A1

公开(公告)日：2008-02-28

申请号：US11781494

申请日：2007-07-23

申请人： Chan-Yong Park ,  Gi-Joon Nam ,  Jung-Won Park ,  In-Ha Kim ,  June-Sun Kim ,  Il-Gun Seo ,  Gun-Joo Lee

发明人： Chan-Yong Park ,  Gi-Joon Nam ,  Jung-Won Park ,  In-Ha Kim ,  June-Sun Kim ,  Il-Gun Seo ,  Gun-Joo Lee

IPC分类号： H01B7/17

CPC分类号： H01B11/1869 ,  H01B11/12

摘要： A micro coaxial cable includes an inner conductor; an insulation layer having foaming cells and formed to surround the inner conductor; an over-foaming preventing layer formed to surround the insulation layer for the purpose of uniform forming of the foaming cells; a metal shield layer formed to surround the over-foaming preventing layer; and a protective coating layer formed to surround the metal shield layer. The over-foaming preventing layer restrains abnormal growth of foaming cells formed in the insulation layer such that the foaming cells are successively adjacently formed with uniform size. Due to the uniformity of foaming, the dielectric constant of the insulation layer is not locally different but uniform as a whole, thereby capable of improving transmission characteristics. In addition, the micro coaxial cable enables to transmit signals even at a high frequency transmission of GHz range, which was impossible in the prior art.

摘要翻译： 微同轴电缆包括内导体; 具有发泡单元并形成为围绕所述内部导体的绝缘层; 为了均匀地形成发泡孔而形成为围绕绝缘层的过度发泡防止层; 形成为包围防止发泡层的金属屏蔽层; 以及形成为围绕金属屏蔽层的保护涂层。 发泡防止层抑制在绝缘层中形成的发泡细胞的异常生长，使得发泡细胞相继形成均匀的尺寸。 由于发泡的均匀性，绝缘层的介电常数并不是局部不同的，而是整体上均匀，从而能够改善传输特性。 此外，微同轴电缆即使在GHz范围的高频率传输也能够传输信号，这在现有技术中是不可能的。

公开(公告)号：US20070044994A1

公开(公告)日：2007-03-01

申请号：US11511755

申请日：2006-08-28

申请人： Chan-Yong Park ,  Jong-Seb Baeck ,  Gi-Joon Nam ,  Woo-Yong Dong

发明人： Chan-Yong Park ,  Jong-Seb Baeck ,  Gi-Joon Nam ,  Woo-Yong Dong

IPC分类号： H01B7/00

CPC分类号： H01B11/06

摘要： A communication cable includes a separator prepared in the cable for preventing alien crosstalk, and at least one spacer integrally formed with the separator at a side of the separator contacting with an outside jacket. The spacer forms a protrusion protruded out on the cable, and this protrusion makes the transmission wires in the cable be spaced apart from adjacent cables. Thus, alien crosstalk generated due to proximity of other cables during high frequency signal transmission may be prevented.

摘要翻译： 通信电缆包括在电缆中制备的用于防止外来串扰的分离器，以及与分离器一体形成的至少一个与外部护套接触的隔板一侧的间隔件。 间隔件形成在电缆上突出的突起，并且该突起使电缆中的传输线与相邻电缆间隔开。 因此，可以防止在高频信号传输期间由于其它电缆的接近而产生的外来串扰。

公开(公告)号：US06877040B1

公开(公告)日：2005-04-05

申请号：US09624716

申请日：2000-07-25

申请人： Gi-Joon Nam ,  Sandor S. Kalman ,  Jason H. Anderson ,  Rajeev Jayaraman ,  Sudip K. Nag ,  Jennifer Zhuang

发明人： Gi-Joon Nam ,  Sandor S. Kalman ,  Jason H. Anderson ,  Rajeev Jayaraman ,  Sudip K. Nag ,  Jennifer Zhuang

IPC分类号： G06F15/173

CPC分类号： G06F17/5077 ,  G06F17/5054

摘要： A method and apparatus for determining routing feasibility of a plurality of nets. Each net has an associated set of one or more routing solutions, wherein each solution specifies one or more routing resources consumed by the net. A liveness Boolean function is generated having variables that represent respective net/solution pairs. If there exists a set of values for the variables such that at least one of the variables for each net is logically true, then the liveness function is true. An exclusivity function is generated using the variables that represent the net/solution pairs. If there exists at least one set of values for the variables such that no resource is used is by more than a predetermined number of nets, then the exclusivity function is true. The nets are routable using the provided solutions if there is one set of values for the variables such that both the liveness and exclusivity functions are true.

摘要翻译： 一种用于确定多个网络的路由可行性的方法和装置。 每个网络具有一组或多个路由解决方案，其中每个解决方案指定网络所消耗的一个或多个路由资源。 生成具有表示相应的净/解对对的变量的活力布尔函数。 如果存在一组变量的值，使得每个网络的至少一个变量在逻辑上为真，那么活动函数为真。 使用表示网络/解决方案对的变量生成排他性功能。 如果存在变量的至少一组值，使得没有资源被使用超过预定数量的网络，则排他性功能是真实的。 如果有一组变量的值，使用提供的解决方案，网络可以路由，以使活动和排他性功能都是真实的。

公开(公告)号：US20050015738A1

公开(公告)日：2005-01-20

申请号：US10621950

申请日：2003-07-17

申请人： Charles Alpert ,  Gary Ellis ,  Gi-Joon Nam ,  Paul Villarrubia

发明人： Charles Alpert ,  Gary Ellis ,  Gi-Joon Nam ,  Paul Villarrubia

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5072

摘要： A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and non-latched objects. The algorithm places objects to minimize clock signal delay subject to a constraint on the placement distribution of the latched objects relative to the placement distribution of the non-latched objects. The latched object and non-latched object placement constraints may limit the difference between the latched object center of mass and a non-latched object center of mass. The latched object center of mass equals a sum of size-location products for each latched object divided by the sum of sizes for each latched object. The constraints may require that the latched object center of mass and the non-latched center of mass both equal the center of mass for all objects.

摘要翻译： 一种设计集成电路的方法，包括执行放置算法以将一组对象放置在集成电路内。 对象集包括锁存对象和非锁定对象。 该算法使对象最小化时钟信号延迟，受限于锁存对象相对于非锁定对象的位置分布的位置分布。 锁定对象和非锁定对象放置约束可能会限制被锁定的物体质心和未锁定的物体质心之间的差异。 被锁定的物体质心等于每个被锁定物体的大小位置乘积之和除以每个锁定物体的大小之和。 约束可能要求被锁定的物体质心和非锁定质心均等于所有物体的质心。

公开(公告)号：US08595675B1

公开(公告)日：2013-11-26

申请号：US13539428

申请日：2012-06-30

申请人： Charles J. Alpert ,  Myung-Chul Kim ,  Gi-Joon Nam ,  Shyam Ramji ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Myung-Chul Kim ,  Gi-Joon Nam ,  Shyam Ramji ,  Natarajan Viswanathan

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5072

摘要： A global placement phase of physical design of an integrated circuit includes iteratively spreading a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and optimizing module placement by preserving global module density while improving a local objective, such as local wirelength and/or local density, in individual subareas among a plurality of subareas of the die area. After global placement, detailed placement of modules in the plurality of subareas is performed.

摘要翻译： 集成电路的物理设计的全局放置阶段包括基于多个模块的密度迭代地扩展包含该集成电路的多个模块，并且通过保持全局模块密度来优化模块放置，同时改善本地目标，例如 作为模具区域的多个子区域中的各个子区域中的局部线长度和/或局部密度。 在全局放置之后，执行在多个子区域中的模块的详细放置。

公开(公告)号：US20130086543A1

公开(公告)日：2013-04-04

申请号：US13248711

申请日：2011-09-29

申请人： Kanak Behari Agarwal ,  Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Natarajan Viswanathan

发明人： Kanak Behari Agarwal ,  Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.

摘要翻译： 在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。 执行细胞运动的全局阶段。 执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位 在为IC设计制作最终布局之前。

公开(公告)号：US08347249B2

公开(公告)日：2013-01-01

申请号：US12416754

申请日：2009-04-01

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Natarajan Viswanathan

IPC分类号： G06F9/455

CPC分类号： G06F17/505

摘要： Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path. The EDA system legalizes the components on a net having a pin selected from the first pin and the second pin. The EDA system determines whether a component is a non-critical component. The EDA system, responsive to a determination that component is a non-critical component, legalizes the non-critical component. The EDA system incrementally optimizes a time delay of the plurality of paths, responsive to legalizing.

摘要翻译： 公开了一种计算机实现的方法，数据处理系统和计算机程序产品，以优化，递增地进行电路设计。 电子设计自动化（EDA）系统接收多个网络，其中每个网络由至少一个引脚组成。 每个销连接到网以形成至少第一销和第二销的路径，其中第一销是第一网的成员。 第二个引脚可以是第二个网络的一个成员，并且该路径与一个松弛相关联。 EDA系统确定路径是否是基于松弛的关键路径。 响应于确定路径是关键路径，EDA系统减少路径的至少一个线长度。 EDA系统移动非关键部件，以便响应于减少路径的至少一个线长度来减少包括非关键部件的引脚的网络的至少一个线长度，其中非关键部件缺少 关键路径上的引脚。 EDA系统使具有从第一引脚和第二引脚选择的引脚的网络上的部件合法化。 EDA系统确定组件是否是非关键组件。 EDA系统响应于组件是非关键组件的确定，使非关键组件合法化。 响应于合法化，EDA系统递增地优化多个路径的时间延迟。

公开(公告)号：US20120284733A1

公开(公告)日：2012-11-08

申请号：US13550957

申请日：2012-07-17

申请人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

发明人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

IPC分类号： G06F9/46

CPC分类号： G06F17/50 ,  G06F9/5066

摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

摘要翻译： 区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。 对于少量的移动端口，通过平衡可放置对象来分配计算。 对于每次移动的少量对象，通过平衡移动端口分配计算。 如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。 对于对象平衡，移动端口被分配给一个处理器，直到处理器的摊销对象数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。 对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。 本发明提供多项式时间的时间表，同时保持高质量的结果。

公开(公告)号：US07467369B2

公开(公告)日：2008-12-16

申请号：US11554235

申请日：2006-10-30

申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia

发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5072

摘要： The illustrative embodiments provide a computer implemented method which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. the process computes a weighted total wire length incremented value for the transformed data set. Further, the process continues by evaluating arrival time constraints, electrical constraints, and user configurable move limits for violations, and restoring the move cells to the original placement if a violation is found.

摘要翻译： 说明性实施例提供了一种计算机实现的方法，其执行减小总线长度的小区变换，而不降低设备定时或违反电气约束。 该过程计算数据集的延迟约束系数。 该过程通过移动单元的子集来执行详细的放置变换，使得放置合法，计算作为网络子集成员的每个输出网的半周长线长度变化，以及计算每个源 - 移动细胞内的宿闸对。 该过程计算用于变换数据集合的加权总线长度递增值。 此外，该过程通过评估抵达时间约束，电气约束和用户可配置的违规移动限制，以及如果发现违规，则将移动单元恢复到原始位置继续。