公开(公告)号：US20130086543A1

公开(公告)日：2013-04-04

申请号：US13248711

申请日：2011-09-29

申请人： Kanak Behari Agarwal ,  Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Natarajan Viswanathan

发明人： Kanak Behari Agarwal ,  Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.

摘要翻译： 在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。 执行细胞运动的全局阶段。 执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位 在为IC设计制作最终布局之前。

公开(公告)号：US08495548B2

公开(公告)日：2013-07-23

申请号：US13248711

申请日：2011-09-29

申请人： Kanak Behari Agarwal ,  Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Natarajan Viswanathan

发明人： Kanak Behari Agarwal ,  Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.

摘要翻译： 在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。 执行细胞运动的全局阶段。 执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位 在为IC设计制作最终布局之前。

公开(公告)号：US08458634B2

公开(公告)日：2013-06-04

申请号：US12912919

申请日：2010-10-27

申请人： Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David Anthony Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

发明人： Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David Anthony Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/62

摘要： A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.

摘要翻译： 一种用于与本地时钟缓冲器（LCB）接近的锁存器聚类的方法，系统和计算机可用程序产品，其中使用算法将多个锁存器聚集成集成电路中的第一组多个组。 确定第一组多个群集锁存器中的多个组。 添加多个LCB，其中添加的LCB的数量与第一组中的组的数量相同。 确定第一组多个聚集锁存器的子集的簇半径，该子集中的组具有作为该子集中的最大簇半径的簇半径。 响应于最大簇半径超过半径阈值，将多个锁存器重新聚集成第二组，第二组群超过第一组多组。

公开(公告)号：US20120110532A1

公开(公告)日：2012-05-03

申请号：US12912919

申请日：2010-10-27

申请人： Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David Anthony Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

发明人： Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David Anthony Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/62

摘要： A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.

摘要翻译： 一种用于与本地时钟缓冲器（LCB）接近的锁存器聚类的方法，系统和计算机可用程序产品，其中使用算法将多个锁存器聚集成集成电路中的第一组多个组。 确定第一组多个群集锁存器中的多个组。 添加多个LCB，其中添加的LCB的数量与第一组中的组的数量相同。 确定第一组多个聚集锁存器的子集的簇半径，该子集中的组具有作为该子集中的最大簇半径的簇半径。 响应于最大簇半径超过半径阈值，将多个锁存器重新聚集成第二组，第二组群超过第一组多组。

公开(公告)号：US20120297355A1

公开(公告)日：2012-11-22

申请号：US13112098

申请日：2011-05-20

申请人： Charles Jay Alpert ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod Alexander Roy ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles Jay Alpert ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod Alexander Roy ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method, system, and computer program product for whitespace creation and preservation in the design of an integrated circuit (IC) are provided in the illustrative embodiments. A first estimate is formed by estimating an amount of whitespace that is needed to reduce a congestion value of a congested area of the design to a threshold value. A set of virtual filler cells is added to the congested area, wherein adding the set of virtual filler cells does not add actual whitespace cells to the congested area but reduces the congested area by at least the first estimate. A virtual filler cell in the set of virtual filler cells is replaced with a corresponding real filler cell. A determination is made whether the design has improved. A final placement solution is created when the design has not improved.

摘要翻译： 在说明性实施例中提供了用于集成电路（IC）设计中的空白创建和保存的方法，系统和计算机程序产品。 通过估计将设计的拥塞区域的拥塞值减少到阈值所需的空白量来形成第一估计。 将一组虚拟填充单元添加到拥塞区域，其中添加虚拟填充单元组不会向拥塞区域添加实际空白单元，而是至少通过第一估计减少拥塞区域。 虚拟填充单元组中的虚拟填充单元被替换为相应的真实填充单元。 确定设计是否改进。 当设计没有改进时，创建最终的布局解决方案。

公开(公告)号：US08347249B2

公开(公告)日：2013-01-01

申请号：US12416754

申请日：2009-04-01

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Natarajan Viswanathan

IPC分类号： G06F9/455

CPC分类号： G06F17/505

摘要： Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path. The EDA system legalizes the components on a net having a pin selected from the first pin and the second pin. The EDA system determines whether a component is a non-critical component. The EDA system, responsive to a determination that component is a non-critical component, legalizes the non-critical component. The EDA system incrementally optimizes a time delay of the plurality of paths, responsive to legalizing.

摘要翻译： 公开了一种计算机实现的方法，数据处理系统和计算机程序产品，以优化，递增地进行电路设计。 电子设计自动化（EDA）系统接收多个网络，其中每个网络由至少一个引脚组成。 每个销连接到网以形成至少第一销和第二销的路径，其中第一销是第一网的成员。 第二个引脚可以是第二个网络的一个成员，并且该路径与一个松弛相关联。 EDA系统确定路径是否是基于松弛的关键路径。 响应于确定路径是关键路径，EDA系统减少路径的至少一个线长度。 EDA系统移动非关键部件，以便响应于减少路径的至少一个线长度来减少包括非关键部件的引脚的网络的至少一个线长度，其中非关键部件缺少 关键路径上的引脚。 EDA系统使具有从第一引脚和第二引脚选择的引脚的网络上的部件合法化。 EDA系统确定组件是否是非关键组件。 EDA系统响应于组件是非关键组件的确定，使非关键组件合法化。 响应于合法化，EDA系统递增地优化多个路径的时间延迟。

公开(公告)号：US08418108B2

公开(公告)日：2013-04-09

申请号：US13162806

申请日：2011-06-17

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan ,  Brian C. Wilson

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan ,  Brian C. Wilson

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031 ,  G06F2217/84

摘要： The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.

摘要翻译： 通过将默认转换速率分配给先前逻辑级的输出门，该值大于设计的中间转换速率来计算集成电路设计选定门的输入。 该默认转换速率通过逻辑级传播，以在所选择的门产生输入转换速率。 默认转换速率对应于应用于设计中随机选择的门的初步压摆率的有限样本的预定百分位数。 作为第二逻辑级中从输出门到第一门的线长度的已知特性的函数调整默认转换速率。 基于输入转换速率来计算所选择的门的延迟。 输入转换速率可以在一次优化迭代期间存储，并在以后的优化迭代中用作默认转换速率。

公开(公告)号：US20110302545A1

公开(公告)日：2011-12-08

申请号：US12796501

申请日：2010-06-08

申请人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块，其中某些图块具有单元格。 扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。 扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。 扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。 扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

公开(公告)号：US20120124539A1

公开(公告)日：2012-05-17

申请号：US12947445

申请日：2010-11-16

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

摘要翻译： 提供了一种用于通过本地时钟缓冲器控制优化进行码头优化的物理综合工具。 物理合成流程包括延迟时钟路由的曝光，直到时钟优化放置阶段为止。 物理综合工具克隆了第一个本地时钟缓冲区。 然后，物理综合工具对整个设计运行时序分析，以计算这一必然破坏性步骤的影响。 在克隆本地时钟缓冲器之后，物理综合工具增加了一个额外的优化步骤来对驱动本地时钟缓冲器的控制信号进行目标。 该优化步骤可以包括锁存克隆，定时驱动放置，缓冲器插入和重新供电。 该流程减轻了高扇出网络，并显着提高了进入时钟优化布局的时间。 放置后，物理综合工具将锁存器和本地时钟缓冲器固定到位，插入时钟路由并释放本地时钟缓冲区。

公开(公告)号：US08347257B2

公开(公告)日：2013-01-01

申请号：US12796501

申请日：2010-06-08

申请人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块，其中某些图块具有单元格。 扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。 扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。 扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。 扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。