公开(公告)号：US08045448B2

公开(公告)日：2011-10-25

申请号：US12189931

申请日：2008-08-12

申请人： Kyu-Min Kang ,  Sang-In Cho ,  Sangsung Choi

发明人： Kyu-Min Kang ,  Sang-In Cho ,  Sangsung Choi

IPC分类号： H04J11/00

CPC分类号： H04L27/2647

摘要： Provided is an apparatus and method for detecting a packet of a zero-padded OFDM signal, which are capable of determining if a packet exists in a reception (RX) signal by comparing a cross-correlation value of an OFDM signal delayed by a predetermined sample time, e.g., a zero-padded sample time, with a power value of the RX signal, thereby increasing a packet detection probability and preventing a false alarm. The packet detecting apparatus includes: a cross-correlation calculator for calculating a cross-correlation value of a reception signal received from the outside and delaying the calculated cross-correlation value by a predetermined sample time; a power calculator for calculating a power value of the reception signal; and a packet detector for determining if a packet exists in the reception signal by comparing the delayed cross-correlation value with the calculated power value, and detecting the corresponding packet.

摘要翻译： 提供了一种检测零填充OFDM信号的分组的装置和方法，其能够通过比较延迟了预定样本的OFDM信号的互相关值来确定在接收（RX）信号中是否存在分组 时间，例如零填充采样时间，具有RX信号的功率值，从而增加分组检测概率并防止误报。 分组检测装置包括：互相关计算器，用于计算从外部接收的接收信号的互相关值，并将所计算的互相关值延迟预定采样时间; 功率计算器，用于计算接收信号的功率值; 以及分组检测器，用于通过将延迟的互相关值与所计算的功率值进行比较来确定接收信号中是否存在分组，并检测相应的分组。

公开(公告)号：US20060126671A1

公开(公告)日：2006-06-15

申请号：US11260591

申请日：2005-10-27

申请人： Seong Park ,  Sangsung Choi ,  Kwang Park

发明人： Seong Park ,  Sangsung Choi ,  Kwang Park

IPC分类号： H04J3/16 ,  H04J3/06

CPC分类号： H04J3/0676 ,  H04J3/0638

摘要： A cycle time synchronization apparatus for a wireless 1394 system having one wireless 1394 intermediary and at least one wireless 1394 slave, the apparatus including: a cycle time generator for generating a cycle time by a predetermined clock signal; a cycle time register synchronized to a beacon inputted, and storing the cycle time from the cycle time generator; a cycle time temporary storage unit for storing the cycle time of the cycle time register and cycle times generated from other devices; a cycle time management unit for managing calculation and control operations of the cycle times of the cycle time register and the cycle time temporary storage unit; and a cycle time controller for controlling the cycle time by the cycle time management unit.

摘要翻译： 一种具有一个无线1394中间和至少一个无线1394从机的无线1394系统的周期时间同步装置，该装置包括：周期时间发生器，用于通过预定时钟信号产生周期时间; 与输入的信标同步的周期时间寄存器，存储来自周期时间发生器的周期时间; 周期时间临时存储单元，用于存储从其他设备产生的周期时间寄存器和周期时间的周期时间; 周期时间管理单元，用于管理周期时间寄存器和周期时间临时存储单元的周期时间的计算和控制操作; 以及循环时间控制器，用于通过循环时间管理单元控制循环时间。

公开(公告)号：US20060093052A1

公开(公告)日：2006-05-04

申请号：US11264886

申请日：2005-11-02

申请人： Sang Cho ,  Sangsung Choi ,  Kwang Park

发明人： Sang Cho ,  Sangsung Choi ,  Kwang Park

IPC分类号： H04K1/10

CPC分类号： H04L27/265 ,  H04L27/263

摘要： A 2N-point and N-point FFT/IFFT dual mode processor is provided. The processor includes a butterfly operator, the first and second MUXs, and the first and second N-point FFT processors. The butterfly operator receives 2N data and butterfly-operates on the received 2N data when receiving a control signal ‘0’ from the controller. The first and second MUXs respectively receive results from the butterfly operator to output the results in an increment of N when receiving a control signal ‘0’ from the controller, and respectively outputs different N data when receiving a control signal ‘1’ from the controller. The first and second N-point FFT processors N-point FFT operate on the results from the first and second MUXs and respectively output the same under control of the controller. Since the N-point FFT operation can be simultaneously performed two times at a receiver, the performance of the receiver can be enhanced.

摘要翻译： 提供2N点和N点FFT / IFFT双模式处理器。 处理器包括蝶形运算符，第一和第二MUX以及第一和第二N点FFT处理器。 当从控制器接收到控制信号“0”时，蝶形运算符接收2N个数据并对接收的2N数据进行蝶形运算。 当从控制器接收到控制信号“0”时，第一和第二MUX分别接收蝶形运算器的结果以输出N的增量，并且当从控制器接收到控制信号“1”时分别输出不同的N数据 。 第一和第二N点FFT处理器N点FFT对来自第一和第二MUX的结果进行操作，并在控制器的控制下分别输出。 由于在接收机可以同时进行N点FFT运算两次，所以可以提高接收机的性能。

公开(公告)号：USRE44413E1

公开(公告)日：2013-08-06

申请号：US12904718

申请日：2010-10-14

申请人： Kyu Min Kang ,  Bub Joo Kang ,  Sangsung Choi ,  Kwang Roh Park

发明人： Kyu Min Kang ,  Bub Joo Kang ,  Sangsung Choi ,  Kwang Roh Park

IPC分类号： H04B1/10

CPC分类号： H04B1/7176 ,  H04B1/7174 ,  H04B2201/70707

摘要： An FIR filter of a DS-CDMA UWB modem transmitter and a control method thereof are disclosed. The FIR filter includes an LUT control device for outputting a resultant value of “0” to all adders if data values corresponding to upper three chips H2, M2 and L2 and lower three chips H, M and L are “000000”, and discriminating which group between a first group and a second group the upper/lower data values belong to if the upper/lower data values are not“000000”. The LUT control device provides upper or lower LUT values to the adders using the upper or lower LUT values as they are, or converts the upper or lower LUT values into 2's complements and provides the converted values to the adders according to the discriminated first or second group.

摘要翻译： 公开了DS-CDMA UWB调制解调发射机的FIR滤波器及其控制方法。 FIR滤波器包括LUT控制装置，用于如果对应于上三个码片H2，M2和L2以及较低三个码片H，M和L的数据值为“000000”，则将所得到的值“0”输出到所有加法器，并且鉴别哪个 如果上/下数据值不是“000000”，则在第一组和第二组之间组合上/下数据值。 LUT控制装置使用上下LUT值向加法器提供上或下LUT值，或者将上或下LUT值转换为2的补码，并根据所识别的第一或第二值向加法器提供转换的值 组。

公开(公告)号：US07693924B2

公开(公告)日：2010-04-06

申请号：US11264886

申请日：2005-11-02

申请人： Sang In Cho ,  Sangsung Choi ,  Kwang Roh Park

发明人： Sang In Cho ,  Sangsung Choi ,  Kwang Roh Park

IPC分类号： G06F17/14

CPC分类号： H04L27/265 ,  H04L27/263

摘要： A 2N-point and N-point FFT/IFFT dual mode processor is provided. The processor includes a butterfly operator, the first and second MUXs, and the first and second N-point FFT processors. The butterfly operator receives 2N data and butterfly-operates on the received 2N data when receiving a control signal ‘0’ from the controller. The first and second MUXs respectively receive results from the butterfly operator to output the results in an increment of N when receiving a control signal ‘0’ from the controller, and respectively outputs different N data when receiving a control signal ‘1’ from the controller. The first and second N-point FFT processors N-point FFT operate on the results from the first and second MUXs and respectively output the same under control of the controller. Since the N-point FFT operation can be simultaneously performed two times at a receiver, the performance of the receiver can be enhanced.

摘要翻译： 提供2N点和N点FFT / IFFT双模式处理器。 处理器包括蝶形运算符，第一和第二MUX以及第一和第二N点FFT处理器。 当从控制器接收到控制信号“0”时，蝶形运算符接收2N个数据并对接收的2N数据进行蝶形运算。 当从控制器接收到控制信号“0”时，第一和第二MUX分别接收蝶形运算器的结果以输出N的增量，并且当从控制器接收到控制信号“1”时分别输出不同的N数据 。 第一和第二N点FFT处理器N点FFT对来自第一和第二MUX的结果进行操作，并在控制器的控制下分别输出。 由于在接收机可以同时进行N点FFT运算两次，所以可以提高接收机的性能。

公开(公告)号：US07623562B2

公开(公告)日：2009-11-24

申请号：US11065570

申请日：2005-02-25

申请人： Kyu Min Kang ,  Bub Joo Kang ,  Sangsung Choi ,  Kwang Roh Park ,  Chae Kyu Kim ,  Jeong Goo Lee

发明人： Kyu Min Kang ,  Bub Joo Kang ,  Sangsung Choi ,  Kwang Roh Park ,  Chae Kyu Kim ,  Jeong Goo Lee

IPC分类号： H04B1/69

CPC分类号： H04B1/71637 ,  H04B1/7075 ,  H04B1/7183

摘要： Provided are an initial synchronization acquiring device and method in a parallel processed DS-CDMA UWB system and a DS-CDMA UWB system's receiver using the same. The initial synchronization acquiring device is constructed to include a correlator for correlating input signals and outputting correlation result values and an initial synchronizer for tuning initial symbol synchronization and frame synchronization by using the correlation result values received from the correlator and then storing combining mark values and a synchronization position value in a register, thereby making it possible to greatly decrease a system's complexity, compared to the existing method of separately designing respective modules for acquiring packet synchronization and symbol synchronization in the existing CDMA system. Also, the initial synchronization acquiring device and method additionally compensates a synchronization error caused by a frequency offset generated between clocks used by a transmitter and a receiver and thereby can be efficiently used in the high-speed and parallel-processed DS-CDMA UWB system.

摘要翻译： 提供了一种并行处理的DS-CDMA UWB系统中的初始同步获取装置和方法，以及使用其的DS-CDMA UWB系统的接收机。 初始同步获取装置被构造为包括用于使输入信号相关并输出相关结果值的相关器和用于通过使用从相关器接收的相关结果值来调整初始符号同步和帧同步的初始同步器，然后存储组合标记值和 与现有CDMA系统中分别设计用于获取分组同步和符号同步的各个模块的现有方法相比，寄存器中的同步位置值可以大大降低系统的复杂度。 此外，初始同步获取装置和方法还补偿由发射机和接收机使用的时钟之间产生的频率偏移引起的同步误差，从而可以在高速和并行处理的DS-CDMA UWB系统中有效地使用。

公开(公告)号：US07505483B2

公开(公告)日：2009-03-17

申请号：US11071200

申请日：2005-03-04

申请人： Yong Ae Jeon ,  Ji Eun Kim ,  Sangsung Choi

发明人： Yong Ae Jeon ,  Ji Eun Kim ,  Sangsung Choi

IPC分类号： H04J3/22

CPC分类号： H04W72/1263 ,  H04L47/14 ,  H04L47/50 ,  H04W84/18

摘要： An apparatus for transmitting WPAN (Wireless Personal Area Network) MAC (Medium Access Control) frames includes a transport frame management unit for creating MAC transport frames if data is generated from an upper protocol and application layer unit, classifying the created MAC transport frames by kinds, and managing the classified MAC transport frames by queues, a transport memory control unit for transmitting the transport frames at a high speed, and a transport frame transmission unit for responsible for the transmission of the transport frames by judging the transmission time of the frames.

摘要翻译： 用于发送WPAN（无线个域网）MAC（媒体接入控制）帧的装置包括：传输帧管理单元，用于如果从上层协议和应用层单元生成数据，则创建MAC传输帧，对所创建的MAC传输帧进行分类 以及通过队列管理分类的MAC传输帧，用于高速传输传输帧的传输存储器控制单元和用于通过判断帧的传输时间负责传输帧的传输的传输帧传输单元。

公开(公告)号：US07382822B2

公开(公告)日：2008-06-03

申请号：US11063583

申请日：2005-02-24

申请人： Bub Joo Kang ,  Kyu Min Kang ,  Sangsung Choi ,  Kwang Roh Park

发明人： Bub Joo Kang ,  Kyu Min Kang ,  Sangsung Choi ,  Kwang Roh Park

IPC分类号： H04B1/00

CPC分类号： H04B1/70735 ,  H04B1/7077 ,  H04B1/7183

摘要： There is provided a code acquisition device and method using a two-step search process in a DS-CDMA UWB modem. The device includes: an I/Q channel symbol generating unit for, generating a plurality (i) of nth I/Q channel symbols in a first search process and generating a plurality of nth I/Q channel symbols in a second search process; a spread code selecting unit for receiving the plurality of nth I/Q channel symbols in the first search process; an NNC2NS tap I/Q channel symbol matched filter unit for, in the second search process, receiving the plurality (i) of nth I/Q channel symbols; a switching unit for changing to a closed state of the second search process; and a super frame and symbol boundary time deciding unit for deciding a super frame time and a symbol boundary time.

摘要翻译： 提供了在DS-CDMA UWB调制解调器中使用两步搜索处理的代码获取装置和方法。 该装置包括：I / Q信道符号生成单元，用于在第一搜索处理中生成第n个第I / Q个信道符号的多个（i），并产生多个第n个 在第二搜索过程中的I / Q通道符号; 扩展码选择单元，用于在第一搜索处理中接收多个第n个I / Q信道符号; 用于在第二搜索过程中，接收多个（i）个第n个/第N个N / N个抽头I / Q通道符号匹配滤波器单元， SUB> I / Q通道符号; 用于切换到第二搜索处理的关闭状态的切换单元; 以及用于决定超帧时间和符号边界时间的超帧和符号边界时间决定单元。

公开(公告)号：US07042401B2

公开(公告)日：2006-05-09

申请号：US11024568

申请日：2004-12-28

申请人： Jong-Kweon Park ,  Bong-Hyuk Park ,  Seung-Sik Lee ,  Jae-Young Kim ,  Sangsung Choi ,  Seoung-Hun Lee ,  Jung-Nam Lee

发明人： Jong-Kweon Park ,  Bong-Hyuk Park ,  Seung-Sik Lee ,  Jae-Young Kim ,  Sangsung Choi ,  Seoung-Hun Lee ,  Jung-Nam Lee

IPC分类号： H01Q1/38

CPC分类号： H01Q1/38

摘要： A micro-miniature, light weighted and low cost trapezoid ultra wide antenna having an ultra wide band characteristics and a notch characteristic in 5 GHz WLAN band (5.15–5.35 GHz) is disclosed. The trapezoid ultra wide antenna includes: a dielectric substrate; a trapezoid shaped patch formed at an upper end of a middle line on an upper side of the dielectric substrate; a feeding line formed at a bottom end of the middle line on the upper side of the dielectric substrate for feeding electric power to the trapezoid shaped patch; a matching stub formed between the trapezoid shaped patch and the feeding line for impedance matching between the trapezoid shaped patch and the feeding line; and a ground formed at a side of the feeding line on the upper side of the dielectric substrate.

摘要翻译： 公开了一种具有超宽带特性和5GHz WLAN频带（5.15-5.35GHz）中的陷波特性的微型，轻量级和低成本梯形超宽天线。 梯形超宽天线包括：电介质基片; 形成在电介质基板的上侧的中间线的上端的梯形贴片; 馈电线，形成在电介质基板的上侧的中间线的底端，用于将电力馈送到梯形贴片; 在梯形贴片和用于梯形贴片和馈线之间的阻抗匹配的馈线之间形成的匹配短截线; 以及在电介质基板的上侧的馈电线的一侧形成的接地。

公开(公告)号：US20060083269A1

公开(公告)日：2006-04-20

申请号：US11065570

申请日：2005-02-25

申请人： Kyu Kang ,  Bub Kang ,  Sangsung Choi ,  Kwang Park ,  Chae Kim ,  Jeong Lee

发明人： Kyu Kang ,  Bub Kang ,  Sangsung Choi ,  Kwang Park ,  Chae Kim ,  Jeong Lee

IPC分类号： H04B7/216 ,  H04B1/69

CPC分类号： H04B1/71637 ,  H04B1/7075 ,  H04B1/7183

摘要： Provided are an initial synchronization acquiring device and method in a parallel processed DS-CDMA UWB system and a DS-CDMA UWB system's receiver using the same. The initial synchronization acquiring device is constructed to include a correlator for correlating input signals and outputting correlation result values and an initial synchronizer for tuning initial symbol synchronization and frame synchronization by using the correlation result values received from the correlator and then storing combining mark values and a synchronization position value in a register, thereby making it possible to greatly decrease a system's complexity, compared to the existing method of separately designing respective modules for acquiring packet synchronization and symbol synchronization in the existing CDMA system. Also, the initial synchronization acquiring device and method additionally compensates a synchronization error caused by a frequency offset generated between clocks used by a transmitter and a receiver and thereby can be efficiently used in the high-speed and parallel-processed DS-CDMA UWB system.