公开(公告)号：US08594114B2

公开(公告)日：2013-11-26

申请号：US12129556

申请日：2008-05-29

Applicant: Jon Faue

Inventor： Jon Faue

IPC: H04L12/28 ,  G11C7/10 ,  G11C8/00 ,  G11C8/16 ,  G06F13/362 ,  G06F13/14

CPC classification number: G11C11/4096 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1042 ,  G11C11/4097

Abstract: A bus driver circuit divides an internal data bus for an integrated circuit memory into at least two groups, designated by speed. A faster group of data lines and a slower group of data lines are placed in an interleaved fashion in order to provide a two group shielding solution. At the earliest opportunity following the reception of a read command, the data from memory banks in the memory is sorted into these two groups. For a DDR3 memory, the sorting method is based on the A2 column address, known as C2. All of the data is brought out of the banks in parallel and sorted as it enters the main amplifiers. These main amplifiers are also divided into two groups, faster and slower. Each amplifier then connects to a data line (G-line) of the same group. The clock assigned to the fast group fires right away, thereby connecting the data associated with the fast amplifiers to the fast data group. This data group then proceeds to the output buffers through the entire data path as fast as possible. The second, slower data group is started with a delayed clock signal and proceeds through the data path to the output buffer maintaining a fixed delay. Since the first and second data groups are not switching at the same time they act as shields to one another.

Abstract translation: 总线驱动器电路将用于集成电路存储器的内部数据总线分成由速度指定的至少两组。 以交错方式放置一组更快的数据线和较慢的数据线组，以提供两组屏蔽解决方案。 在接收到读取命令之后的最早的机会中，来自存储器中的存储体的数据被分成这两个组。 对于DDR3内存，排序方法基于A2列地址，称为C2。 所有数据从并行输出，并进入主放大器进行排序。 这些主放大器也分为两组，速度越来越慢。 每个放大器然后连接到同一组的数据线（G线）。 分配给快速组的时钟立即触发，从而将与快速放大器相关联的数据连接到快速数据组。 该数据组然后尽可能快地通过整个数据路径前进到输出缓冲器。 第二个较慢的数据组以延迟的时钟信号开始，并通过数据路径进入到输出缓冲器，保持固定的延迟。 由于第一和第二数据组不同时进行切换，因此它们作为彼此的屏蔽。

公开(公告)号：US20090190410A1

公开(公告)日：2009-07-30

申请号：US12021209

申请日：2008-01-28

Applicant: Jon Faue

Inventor： Jon Faue

IPC: G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  H03K5/08

Abstract: A data capture circuit includes strobes that track input data even when conditions arise that cause the differences in skew from interpreting data state ones and zeros. This is accomplished whether these skews arise from reference voltage variation, data pattern loading, power supply droop, process variations within the chip itself, or other causes. The differential input strobes of the data capture circuit are input into individual input buffers, each compared against a reference voltage individually, as well as a data input pin. The outputs from these buffers are maintained separate from each other all the way to the point where the input data is latched. In latching the input data, data ones are latched entirely based on input signals derived from a rising edge (both strobes and data), and zeros are latched entirely based on input signals derived from a falling edge (both strobes and data).

Abstract translation: 数据采集​​电路包括即使出现导致偏斜差异的情况来解释数据状态1和零的情况下跟踪输入数据的选通。 这是由于参考电压变化，数据模式加载，电源下降，芯片本身内的工艺变化或其他原因引起的。 数据采集​​电路的差分输入选通信号被输入到各个输入缓冲器中，每个输入缓冲器分别与参考电压以及数据输入引脚进行比较。 这些缓冲器的输出保持彼此分离，直到输入数据被锁存的点。 在锁存输入数据时，基于从上升沿（选通脉冲和数据）导出的输入信号，数据锁存完全基于从下降沿（选通脉冲和数据）导出的输入信号完全锁存零。

公开(公告)号：US20060245293A1

公开(公告)日：2006-11-02

申请号：US11456891

申请日：2006-07-12

Applicant: Jon Faue

Inventor： Jon Faue

IPC: G11C8/00

CPC classification number: G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: A clock generator is provided that is compatible with both DDR1 and DDR2 applications. The internal YCLK signal is turned on only when an active read or write occurs on the integrated circuit memory, even though the main chip clock is always running. A circuit block within the clock generator detects when a read or write is active and initiates a YCLK signal on the next falling edge of the internal clock. Two separate mechanisms are used for determining when to terminate the YCLK. One mechanism is a timer path and the other is a path determined by DDR1 and DDR2 control signals. The timer path is strictly time based and is the same for DDR1 and DDR2 parts or modes of operation. The other signal path is different for DDR1 and DDR2 operating modes. A DDR1 control signal turns off YCLK at the next rising edge of the internal clock, and a DDR2 control signal turns off YCLK at the next falling edge of the internal clock.

Abstract translation: 提供与DDR1和DDR2应用兼容的时钟发生器。 即使主芯片时钟始终运行，内部YCLK信号仅在集成电路存储器上发生有效读取或写入时导通。 时钟发生器内的一个电路块检测读或写何时有效，并在内部时钟的下一个下降沿启动YCLK信号。 使用两个单独的机制来确定何时终止YCLK。 一种机制是定时器路径，另一种是由DDR1和DDR2控制信号确定的路径。 定时器路径是基于时间的，对于DDR1和DDR2部件或操作模式是相同的。 DDR1和DDR2操作模式的其他信号路径不同。 DDR1控制信号在内部时钟的下一个上升沿关闭YCLK，DDR2控制信号在内部时钟的下一个下降沿关闭YCLK。

公开(公告)号：US20060044925A1

公开(公告)日：2006-03-02

申请号：US10924546

申请日：2004-08-24

Applicant: Jon Faue ,  Steve Eaton

Inventor： Jon Faue ,  Steve Eaton

IPC: G11C8/00

CPC classification number: G11C7/1066 ,  G11C7/22 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4082

Abstract: A limited output address register technique for selectively variable write latency in double data rate 2 (DDR2) integrated circuit memory devices providing a reduced number of paths directly connected to the output. A chain of DQ flip-flops is disclosed which is only loaded on valid write address commands but shifts continually thereafter every clock cycle. Since new READ or WRITE commands cannot be issued on successive cycles, at any given point in the chain an address (or state) is valid for at least two cycles. Therefore, a selected point in the register chain can be used to satisfy the requirements for two different latencies. For DDR2, having N write latency cases, only ceil(N/2) access points to the write address output have to be provided thereby saving on-chip area and increasing speed. In a specific embodiment disclosed, DDR1 may also be supported.

Abstract translation: 双数据速率2（DDR 2）集成电路存储器件中的有选择地可变写入延迟的有限输出地址寄存器技术，其提供了直接连接到输出端的减少数量的路径。 公开了一系列DQ触发器，其仅加载在有效的写入地址命令上，然后在每个时钟周期之后不断地移动。 由于在连续循环中不能发出新的READ或WRITE命令，所以在链中的任何给定点，地址（或状态）至少有两个周期有效。 因此，可以使用寄存器链中的选定点来满足两个不同延迟的要求。 对于具有N个写延迟情况的DDR2，必须仅提供写入地址输出的ceil（N / 2）接入点，从而节省片上区域并提高速度。 在所公开的具体实施例中，还可以支持DDR 1。