公开(公告)号：US20070091691A1

公开(公告)日：2007-04-26

申请号：US11257610

申请日：2005-10-25

Applicant: Jon Faue ,  Van Butler

Inventor： Jon Faue ,  Van Butler

IPC: G11C7/10

CPC classification number: G06F5/06

Abstract: A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command.

Abstract translation: 一个电路提供了最广泛的窗口，用于捕获数据并防止FIFO寄存器中的溢出。 FIFO寄存器每个I / O包含两个寄存器。 使用两个FIFO输入时钟，每个FIFO寄存器一个。 当一个FIFO时钟激活时，另一个FIFO被自动禁止。 最初，电路复位，使得一个时钟有效，另一个被禁止。 当接收到有效的READ命令时，附加到FICLK当前为低电平的移位链开始计数时钟周期。 这最终确定何时可以启用当前为低电平的FICLK。 最终启用取决于关闭当前高的FICLK。 在复位期间使能的FICLK在与READ命令相关联的YCLK的下降沿之后关闭固定延迟。

公开(公告)号：US20090300255A1

公开(公告)日：2009-12-03

申请号：US12129556

申请日：2008-05-29

Applicant: Jon Faue

Inventor： Jon Faue

IPC: G06F13/14

CPC classification number: G11C11/4096 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1042 ,  G11C11/4097

Abstract: A bus driver circuit divides an internal data bus for an integrated circuit memory into at least two groups, designated by speed. A faster group of data lines and a slower group of data lines are placed in an interleaved fashion in order to provide a two group shielding solution. At the earliest opportunity following the reception of a read command, the data from memory banks in the memory is sorted into these two groups. For a DDR3 memory, the sorting method is based on the A2 column address, known as C2. All of the data is brought out of the banks in parallel and sorted as it enters the main amplifiers. These main amplifiers are also divided into two groups, faster and slower. Each amplifier then connects to a data line (G-line) of the same group. The clock assigned to the fast group fires right away, thereby connecting the data associated with the fast amplifiers to the fast data group. This data group then proceeds to the output buffers through the entire data path as fast as possible. The second, slower data group is started with a delayed clock signal and proceeds through the data path to the output buffer maintaining a fixed delay. Since the first and second data groups are not switching at the same time they act as shields to one another.

Abstract translation: 总线驱动器电路将用于集成电路存储器的内部数据总线分成由速度指定的至少两组。 以交错方式放置一组更快的数据线和较慢的数据线组，以提供两组屏蔽解决方案。 在接收到读取命令之后的最早的机会中，来自存储器中的存储体的数据被分成这两个组。 对于DDR3内存，排序方法基于A2列地址，称为C2。 所有数据从并行输出，并进入主放大器进行排序。 这些主放大器也分为两组，速度越来越慢。 每个放大器然后连接到同一组的数据线（G线）。 分配给快速组的时钟立即触发，从而将与快速放大器相关联的数据连接到快速数据组。 该数据组然后尽可能快地通过整个数据路径前进到输出缓冲器。 第二个较慢的数据组以延迟的时钟信号开始，并通过数据路径进入到输出缓冲器，保持固定的延迟。 由于第一和第二数据组不同时进行切换，因此它们作为彼此的屏蔽。

公开(公告)号：US20060209618A1

公开(公告)日：2006-09-21

申请号：US11071852

申请日：2005-03-03

Applicant: Jon Faue ,  Craig Barnett

Inventor： Jon Faue ,  Craig Barnett

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C7/1066 ,  G11C8/18

Abstract: An additive latency circuit for a DDR2 standard compliant integrated circuit memory includes a half flip-flop register assigned for each case of additive latency. A unique clock is generated to control each bit in the register chain. Sufficient register bits are required in the chain to support the highest additive latency specified. For latency settings less than the maximum, those clocks assigned to the bits above the chosen latency are enabled so the data passes through un-clocked. For the additive latency zero case, a separate bypass path is provided. Both address and command information is delayed by the additive latency delay chain. Once delayed by the proper number of cycles, the address information remains in that state until the time when a new state is required. Command information remains valid for one cycle upon reaching the proper delay point. A reset circuit is provided to reset command signals.

Abstract translation: 用于DDR2标准兼容集成电路存储器的附加延迟电路包括为每种附加延迟情况分配的半触发器寄存器。 产生唯一的时钟来控制寄存器链中的每个位。 链中需要足够的寄存器位来支持指定的最高附加延迟。 对于小于最大值的延迟设置，分配给所选等待时间以上的位的时钟将被启用，以便数据通过非时钟。 对于附加延迟零情况，提供单独的旁路路径。 地址和命令信息都被加法延迟延迟链延迟。 一旦延迟了适当的周期数，地址信息将保持在该状态，直到需要新状态为止。 命令信息在达到适当的延迟点后保持有效。 提供复位电路以复位指令信号。

公开(公告)号：US20060076975A1

公开(公告)日：2006-04-13

申请号：US10960369

申请日：2004-10-07

Applicant: Jon Faue

Inventor： Jon Faue

IPC: H03K19/094

CPC classification number: H03K19/018521

Abstract: A level shifting circuit includes an input node, an output node, a first power supply node, a second power supply node, a third power supply node, an inverter coupled to the first and second power supply nodes having an input coupled to the input node and an output, a transistor having a current path coupled between the output of the inverter an the output node, a first transistor circuit coupled between the first power supply node and the third power supply node having a first input coupled to the output of the inverter, a second input coupled to the output node, and an output, and a second transistor circuit coupled between the output node and the third power supply node having a first input coupled to the output of the first transistor circuit and a second input coupled to the input node.

公开(公告)号：US20050275462A1

公开(公告)日：2005-12-15

申请号：US10868146

申请日：2004-06-15

Applicant: John Heightley ,  Jon Faue

Inventor： John Heightley ,  Jon Faue

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F2200/513 ,  H03F2203/45294 ,  H03F2203/45684

Abstract: A differential amplifier design and bias control technique of particular applicability for low voltage operation in which the threshold voltage of n-channel differential input transistors is controlled using substrate bias in order to allow a wider range of input signal levels. Further disclosed is a technique for controlling the substrate bias of the input transistors of a differential amplifier based on the level of the output of the amplifier in addition to a differential amplifier circuit capable of low voltage operation in which an additional bias current is introduced that enables the output pull-up current to be increased without increasing the pull-down current.

Abstract translation: 用于低电压操作的差分放大器设计和偏置控制技术，其中使用衬底偏置来控制n沟道差分输入晶体管的阈值电压，以便允许更宽范围的输入信号电平。 进一步公开了一种用于基于放大器的输出电平来控制差分放大器的输入晶体管的衬底偏置的技术，除了能够进行低电压操作的差分放大器电路之外，其中引入额外的偏置电流，使得能够 输出上拉电流增加而不增加下拉电流。

公开(公告)号：US20050195679A1

公开(公告)日：2005-09-08

申请号：US10794782

申请日：2004-03-03

Applicant: Jon Faue ,  Steve Eaton

Inventor： Jon Faue ,  Steve Eaton

IPC: G11C7/00 ,  G11C11/34 ,  G11C11/409

CPC classification number: G11C7/1027 ,  G11C7/1042 ,  G11C7/1072 ,  G11C11/4093 ,  G11C11/4096

Abstract: A sorting circuit (140) transfers data between a first group of at least four lines (134) on which the data items are arranged based on their addresses, and a second group of lines (138, WD0R, WD0F, WD1R, WD1F) on which the data items are arranged based on the order in which they are read or written in a burst operation. Six signals (SORT) and their complements are sufficient to control the sorting circuit for both the read and the write operations, and provide both the DDR and the DDR2 functionality.

Abstract translation: 排序电路（140）在基于其地址的数据项目排列的至少四行（134）的第一组和第二组线（138，WD 0 R，WD 0 F，WD 1 R，WD 1 F），根据它们在突发操作中读取或写入的顺序，数据项被布置在其上。 六个信号（SORT）及其补码足以控制读取和写入操作的分类电路，并提供DDR和DDR2功能。

公开(公告)号：US20070008784A1

公开(公告)日：2007-01-11

申请号：US11177537

申请日：2005-07-08

Applicant: Jon Faue ,  Steve Eaton ,  Michael Murray

Inventor： Jon Faue ,  Steve Eaton ,  Michael Murray

IPC: G11C7/10

CPC classification number: G11C7/1078 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/1096

Abstract: A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

Abstract translation: 用于集成电路存储器的数据总线电路包括用于将存储器与I / O块连接的每个I / O焊盘的4位总线，但每个I / O仅使用两位用于写入。 使用四位每个I / O焊盘进行读取。 在输入数据选通的每个下降沿，最后两位通过总线发送，这样就不需要精确计数输入数据选通脉冲。 数据总线电路兼容DDR1和DDR2工作模式。

公开(公告)号：US20060062064A1

公开(公告)日：2006-03-23

申请号：US10948554

申请日：2004-09-23

Applicant: Jon Faue

Inventor： Jon Faue

IPC: G11C7/00

CPC classification number: G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: A clock generator is provided that is compatible with both DDR1 and DDR2 applications. The internal YCLK signal is turned on only when an active read or write occurs on the integrated circuit memory, even though the main chip clock is always running. A circuit block within the clock generator detects when a read or write is active and initiates a YCLK signal on the next falling edge of the internal clock. Two separate mechanisms are used for determining when to terminate the YCLK. One mechanism is a timer path and the other is a path determined by DDR1 and DDR2 control signals. The timer path is strictly time based and is the same for DDR1 and DDR2 parts or modes of operation. The other signal path is different for DDR1 and DDR2 operating modes. A DDR1 control signal turns off YCLK at the next rising edge of the internal clock, and a DDR2 control signal turns off YCLK at the next falling edge of the internal clock.

Abstract translation: 提供与DDR1和DDR2应用兼容的时钟发生器。 即使主芯片时钟始终运行，内部YCLK信号仅在集成电路存储器上发生有效读取或写入时导通。 时钟发生器内的一个电路块检测读或写何时有效，并在内部时钟的下一个下降沿启动YCLK信号。 使用两个单独的机制来确定何时终止YCLK。 一种机制是定时器路径，另一种是由DDR1和DDR2控制信号确定的路径。 定时器路径是基于时间的，对于DDR1和DDR2部件或操作模式是相同的。 DDR1和DDR2操作模式的其他信号路径不同。 DDR1控制信号在内部时钟的下一个上升沿关闭YCLK，DDR2控制信号在内部时钟的下一个下降沿关闭YCLK。

公开(公告)号：US20060023529A1

公开(公告)日：2006-02-02

申请号：US10893783

申请日：2004-07-16

Applicant: Jon Faue ,  John Heightley

Inventor： Jon Faue ,  John Heightley

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C7/1048

Abstract: An equalization circuit for a pair of resistive-capacitive data lines includes primary and secondary equalization circuits attached at both ends of the data line pair. A primary equalization circuit at one end of the data line pair receives a primary control signal, and a secondary equalization circuit at the other end of the data line pair receives a secondary control signal, which is different than the primary control signal. The equalization devices in the primary equalization circuit are attached near the read and write amplifiers and operate normally since all the information is available as to whether or not the corresponding data line pair should be equalized. The additional equalization devices in the secondary equalization circuit placed at the other end of the data line pair receive a simpler control signal that lacks the information as to whether or not any particular data line pair is being equalized.

Abstract translation: 用于一对电阻电容数据线的均衡电路包括连接在数据线对的两端的主和次级均衡电路。 数据线对一端的主均衡电路接收主控信号，数据线对另一端的二次均衡电路接收与主控信号不同的二次控制信号。 一次均衡电路中的均衡器件附着在读和写放大器附近并且正常工作，因为所有的信息可用于相应的数据线对是否应该相等。 放置在数据线对的另一端的次级均衡电路中的附加均衡装置接收到更简单的控制信号，其缺少关于任何特定数据线对是否被均衡的信息。

公开(公告)号：US20050275461A1

公开(公告)日：2005-12-15

申请号：US10868145

申请日：2004-06-15

Applicant: John Heightley ,  Jon Faue

Inventor： John Heightley ,  Jon Faue

IPC: H03F1/30 ,  H03F3/45

CPC classification number: H03F3/45183 ,  H03F2200/513 ,  H03F2203/45684

Abstract: A differential amplifier design and bias control technique of particular applicability for low voltage operation in which the threshold voltage of n-channel differential input transistors is controlled using substrate bias in order to allow a wider range of input signal levels. Further disclosed is a technique for controlling the substrate bias of the input transistors of a differential amplifier based on the level of the output of the amplifier in addition to a differential amplifier circuit capable of low voltage operation in which an additional bias current is introduced that enables the output pull-up current to be increased without increasing the pull-down current, as well as circuitry for optimizing the performance of the differential in both DDR-I and DDR-II operational modes.

Abstract translation: 用于低电压操作的差分放大器设计和偏置控制技术，其中使用衬底偏置来控制n沟道差分输入晶体管的阈值电压，以便允许更宽范围的输入信号电平。 进一步公开了一种用于基于放大器的输出电平来控制差分放大器的输入晶体管的衬底偏置的技术，除了能够进行低电压操作的差分放大器电路之外，其中引入额外的偏置电流，使得能够 在不增加下拉电流的情况下增加输出上拉电流，以及用于优化DDR-I和DDR-II操作模式中的差分性能的电路。