公开(公告)号：US08259878B2

公开(公告)日：2012-09-04

申请号：US12630056

申请日：2009-12-03

申请人： Chanho Yoon ,  Hun-Sik Kang ,  Eun-Young Choi ,  Sok-Kyu Lee

发明人： Chanho Yoon ,  Hun-Sik Kang ,  Eun-Young Choi ,  Sok-Kyu Lee

IPC分类号： H04L27/08

CPC分类号： H04L27/01 ,  H03G3/3052 ,  H04B7/08 ,  H04L27/08 ,  H04L2025/03426

摘要： Provided are apparatus and method for receiving signals in a wireless communication system. A receiving apparatus including a plurality of variable gain amplifier units configured to respectively control the gains of radio frequency (RF) signals received respectively through a plurality of antennas, and a plurality of analog-to-digital converters configured to respectively convert the output signals of the respective variable gain amplifiers into digital signals, includes: an automatic gain controller configured to calculate the gain values of the respective gain control amplifier units by receiving the digital signals outputted from the respective analog-to-digital converters, select the minimum gain value among the calculated gain control values, and calculate the differences between the minimum gain value and the other gain values; and a noise matching amplifier configured to attenuate the digital signals outputted from the respective analog-to-digital converters according to the calculated difference values.

摘要翻译： 提供了一种用于在无线通信系统中接收信号的装置和方法。 一种接收装置，包括：多个可变增益放大器单元，被配置为分别控制分别通过多个天线接收的射频（RF）信号的增益;多个模数转换器，被配置为分别转换 将各个可变增益放大器转换为数字信号，包括：自动增益控制器，被配置为通过接收从各个模数转换器输出的数字信号来计算各个增益控制放大器单元的增益值，选择最小增益值 计算增益控制值，并计算最小增益值与其他增益值之间的差值; 以及噪声匹配放大器，被配置为根据所计算的差值来衰减从各个模数转换器输出的数字信号。

公开(公告)号：US20140366153A1

公开(公告)日：2014-12-11

申请号：US14465509

申请日：2014-08-21

申请人： Chanho Yoon

发明人： Chanho Yoon

IPC分类号： G06F21/60 ,  G06F11/273

CPC分类号： G06F21/60 ,  G06F9/00 ,  G06F11/00 ,  G06F11/273 ,  G06F11/30 ,  G06F11/3089 ,  G06F11/362 ,  G06F11/3648 ,  G06F13/36 ,  G06F13/42 ,  G06F21/00 ,  G06F21/78 ,  H04L9/32 ,  H04L63/00

摘要： A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host.

摘要翻译： 一种设备包括第一总线，第二总线，配置成通过第一总线与存储电路通信并通过第二总线与调试主机进行通信的处理器;以及控制电路，其被配置为禁止将数据从第二总线传送到 所述调试主机在从所述调试主机接收认证信息的同时，以及响应于所接收的认证信息的认证，使得能够将数据从所述第二总线传送到所述调试主机。 控制电路可以被配置为通过使伪数据通过设备和调试主机之间的发送信道发送到调试主机来禁止从第二总线到调试主机的数据传输。

公开(公告)号：US08832843B2

公开(公告)日：2014-09-09

申请号：US12783953

申请日：2010-05-20

申请人： Chanho Yoon

发明人： Chanho Yoon

IPC分类号： G06F7/04 ,  G06F17/30 ,  H04N7/16 ,  G06F11/30 ,  G06F11/36 ,  G06F21/78 ,  H04L9/32 ,  G06F11/00 ,  G06F21/00 ,  G06F13/36 ,  G06F9/00 ,  H04L29/06

CPC分类号： G06F21/60 ,  G06F9/00 ,  G06F11/00 ,  G06F11/273 ,  G06F11/30 ,  G06F11/3089 ,  G06F11/362 ,  G06F11/3648 ,  G06F13/36 ,  G06F13/42 ,  G06F21/00 ,  G06F21/78 ,  H04L9/32 ,  H04L63/00

摘要： A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host.

摘要翻译： 一种设备包括第一总线，第二总线，配置成通过第一总线与存储电路通信并通过第二总线与调试主机进行通信的处理器;以及控制电路，其被配置为禁止将数据从第二总线传送到 所述调试主机在从所述调试主机接收认证信息的同时，以及响应于所接收的认证信息的认证，使得能够将数据从所述第二总线传送到所述调试主机。 控制电路可以被配置为通过使伪数据通过设备和调试主机之间的发送信道发送到调试主机来禁止从第二总线到调试主机的数据传输。

公开(公告)号：US08738838B2

公开(公告)日：2014-05-27

申请号：US13082190

申请日：2011-04-07

申请人： Kyoung Lae Cho ,  Chanho Yoon ,  JunJin Kong ,  Hee Chang Cho ,  Bumseok Yu ,  Hong Rak Son

发明人： Kyoung Lae Cho ,  Chanho Yoon ,  JunJin Kong ,  Hee Chang Cho ,  Bumseok Yu ,  Hong Rak Son

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： H03M7/30 ,  G11C16/349

摘要： A method of storing data in a storage media can include determining whether a size of data to be stored in the storage media satisfies a reference condition and compressing the data to provide compressed data for storage in the storage media upon determining that the size satisfies a reference condition.

摘要翻译： 在存储介质中存储数据的方法可以包括确定要存储在存储介质中的数据的大小是否满足参考条件，并且在确定尺寸满足参考值时，压缩数据以提供用于存储在存储介质中的压缩数据 条件。

公开(公告)号：US08423878B2

公开(公告)日：2013-04-16

申请号：US12758103

申请日：2010-04-12

申请人： WooSeong Cheong ,  Bumseok Yu ,  Chanho Yoon

发明人： WooSeong Cheong ,  Bumseok Yu ,  Chanho Yoon

IPC分类号： G06F11/00

CPC分类号： H03M13/47 ,  G06F11/10 ,  H03M13/6306

摘要： A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.

摘要翻译： 存储器控制器包括被配置为与外部设备交换数据的第一和第二接口控制器以及连接在第一和第二接口控制器之间的内部块。 第一和第二接口控制器通过内部块交换从外部设备接收的数据和对应于接收到的数据的至少一个奇偶校验位。

公开(公告)号：US20100306631A1

公开(公告)日：2010-12-02

申请号：US12758103

申请日：2010-04-12

申请人： WooSeong Cheong ,  Bumseok Yu ,  Chanho Yoon

发明人： WooSeong Cheong ,  Bumseok Yu ,  Chanho Yoon

IPC分类号： H03M13/09 ,  G06F12/00 ,  G06F11/10

CPC分类号： H03M13/47 ,  G06F11/10 ,  H03M13/6306

摘要： A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.

摘要翻译： 存储器控制器包括被配置为与外部设备交换数据的第一和第二接口控制器以及连接在第一和第二接口控制器之间的内部块。 第一和第二接口控制器通过内部块交换从外部设备接收的数据和对应于接收到的数据的至少一个奇偶校验位。

公开(公告)号：US20100299467A1

公开(公告)日：2010-11-25

申请号：US12783953

申请日：2010-05-20

申请人： Chanho Yoon

发明人： Chanho Yoon

IPC分类号： G06F13/36 ,  G06F13/42

CPC分类号： G06F21/60 ,  G06F9/00 ,  G06F11/00 ,  G06F11/273 ,  G06F11/30 ,  G06F11/3089 ,  G06F11/362 ,  G06F11/3648 ,  G06F13/36 ,  G06F13/42 ,  G06F21/00 ,  G06F21/78 ,  H04L9/32 ,  H04L63/00

摘要： A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host.

摘要翻译： 一种设备包括第一总线，第二总线，配置成通过第一总线与存储电路通信并通过第二总线与调试主机进行通信的处理器;以及控制电路，其被配置为禁止将数据从第二总线传送到 所述调试主机在从所述调试主机接收认证信息的同时，以及响应于所接收的认证信息的认证，使得能够将数据从所述第二总线传送到所述调试主机。 控制电路可以被配置为通过使伪数据通过设备和调试主机之间的发送信道发送到调试主机来禁止从第二总线到调试主机的数据传输。